DS89C420_05 Datasheet, PDF (12/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
PIN DESCRIPTION
PIN
DIP
PLCC
TQFP
40
12, 44
6, 38
20
1, 22, 23, 34
16, 17, 28,
39
9
10
4
19
21
15
18
20
14
29
32
26
30
33
27
39
43
37
38
42
36
37
41
35
36
40
34
35
39
33
34
38
32
33
37
31
32
36
30
1–8
2–9
40–44, 1–
3
1
2
40
2
3
41
3
4
42
4
5
43
5
6
44
6
7
1
7
8
2
8
9
3
NAME
VCC
GND
RST
XTAL1
XTAL2
PSEN
ALE/PROG
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P1.0–P1.7
FUNCTION
VCC - +5V
Logic Ground
External Reset. The RST input pin is bidirectional and contains a Schmitt
trigger to recognize external active-high reset inputs. The pin also employs
an internal pulldown resistor to allow for a combination of wire-ORed external
reset sources. An RC is not required for power-up, since the device provides
this function internally.
XTAL1, XTAL2. The crystal oscillator pins XTAL1 and XTAL2 provide support
for fundamental mode parallel resonant, AT cut crystals. XTAL1 also acts as
an input if there is an external clock source in place of a crystal. XTAL2
serves as the output of the crystal amplifier.
Program Store Enable. This signal is commonly connected to optional
external program memory as a chip enable. PSEN provides an active-low
pulse and is driven high when external program memory is not being
accessed. In 1-cycle page mode 1, PSEN remains low for consecutive page
hits.
Address Latch Enable. Functions as a clock to latch the external address LSB
from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. In
default mode, ALE has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. In page mode, the ALE pulse width is altered according to the
page mode selection. In traditional 8051 mode, ALE is high when using the
EMI reduction mode and during a reset condition. ALE can be enabled by
writing ALEON = 1 (PMR.2). Note that ALE operates independently of
ALEON during external memory accesses. As an alternate mode, this pin
(PROG) is used to execute the parallel program function.
Port 0 (AD0–7), I/O. Port 0 is an open-drain 8-bit, bidirectional I/O port. As an
alternate function, Port 0 can function as the multiplexed address/data bus to
access off-chip memory. During the time when ALE is high, the LSB of a
memory address is presented. When ALE falls to a logic 0, the port
transitions to a bidirectional data bus. This bus is used to read external
program memory and read/write external RAM or peripherals. When used as
a memory bus, the port provides weak pullups for logic 1 outputs. The reset
condition of Port 0 is three-state. Pullup resistors are required when using
Port 0 as an I/O port.
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an
alternate functional interface for timer 2 I/O, new external interrupts, and new
serial port 1. The reset condition of port 1 is with all bits at logic 1. In this
state, a weak pullup holds the port high. This condition also serves as an
input state, since any external circuit that writes to the port overcomes the
weak pullup. When software writes a 0 to any port pin, the DS89C420
activates a strong pulldown that remains on until either a 1 is written or a
reset occurs. Writing a 1 after the port has been at 0 causes a strong
transition driver to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes the output high
(and input) state. The alternate functions of Port 1 are outlined below.
PORT ALTERNATE
FUNCTION
P1.0
T2
External I/O for Timer/Counter 2
P1.1
T2EX
Timer 2 Capture/Reload Trigger
P1.2
RXD1
Serial Port 1 Receive
P1.3
TXD1
Serial Port 1 Transmit
P1.4
INT2
External Interrupt 2 (Positive Edge Detect)
P1.5
INT3
External Interrupt 3 (Negative Edge Detect)
P1.6
INT4
External Interrupt 4 (Positive Edge Detect)
P1.7
INT5
External Interrupt 5 (Negative Edge Detect)
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