DS89C420_05 Datasheet, PDF (37/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Before these bits can be altered, the processor must execute the timed access sequence. This sequence consists
of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three
machine cycles. This timed sequence of steps then allows any of the timed-access-protected SFR bits to be altered
during the three machine cycles, following the writing of the 55h. Writing to a timed access-protected bit outside of
these three machine cycles has no effect on the bit.
The timed-access process is address-, data-, and time-dependent. A processor running out of control and not
executing system software cannot statistically perform this timed sequence of steps, and as such, will not
accidentally alter the protected bits. It should be noted that this method should be used in the main body of the
system software and never used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines
using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the
watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. It is
advisable that interrupts be disabled (EA = 0) when executing the timed-access sequence, since an interrupt during
the sequence adds time, making the timed-access attempt fail.
POWER MANAGEMENT AND CLOCK-DIVIDE CONTROL
The DS89C420 incorporates power management features that monitor the power-supply voltage levels and
support low-power operation with three power-saving modes. Such features include a bandgap voltage monitor,
watchdog timer, selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide
control and application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE,
E8h), extended interrupt flag (EXIF, 91h), and power control (PCON, 87h) registers.
SYSTEM CLOCK-DIVIDE CONTROL
The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to
different crystals and also to slow the system clocks providing lower power operation when required. An on-chip
crystal multiplier allows the DS89C420 to operate at two or four times the crystal frequency by setting the 4X/2X bit
and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024.
When used with a 7.372MHz crystal, for example, the processor executes machine cycle in times ranging from
33.9ns (divide-by-0.25) to 138.9ms (multiply-by-1024), and maintains a highly accurate serial port baud rate while
allowing the use of more cost-effective, lower-frequency crystals. Although the clock-divide control bits can be
written at any time, certain hardware features have been provided to enhance the use of these clock controls to
guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. The
01b setting of CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock
into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset.
When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the system
forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has
detected externally enabled interrupts.
The oscillator divide ratios of 0.25, 0.5, and 1 are also used to provide standard baud-rate generation for the serial
ports through a forced divide-by-12 input clock (TxMH, TxM = 00b, x = 1, 2, or 3) to the timers.
When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system
uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This
automatic switchback is only enabled during divide-by-1024 mode, and all other clock modes are unaffected by
interrupts and serial port activity. See Power Management Mode for more details.
Use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal multiplier be
enabled and the specific system-clock-multiply value be established by the 4X/2X bit in the PMR register. The
multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup delay has
been established through the CKRY bit in the status register. The 4X/2X bit can only be altered when the CTM bit is
cleared to logic 0. This prevents the system from changing the multiplier until the system has moved back to the
divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered when
the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to logic 1
from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup
timeout in the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the
CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to logic 0 on all resets. Figure 15 gives a
37 of 47