DS89C420_05 Datasheet, PDF (25/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
The SEL (DPS.0) bit always selects the active data pointer. The DS89C420 offers a programmable option that
allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting
the toggle-select-enable bit (TSL-DPS.5) to logic 1. Once enabled, the SEL bit is automatically toggled after the
execution of one of the following five DPTR-related instructions:
INC DPTR
MOV DPTR #data16
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
The DS89C420 also offers a programmable option that automatically increases (or decreases) the contents of the
selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or
decrement) is dependent upon the setting of the ID1 and ID0 bits. This option is enabled by setting the automatic
increment/decrement enable (AID-DPS.4) to a logic 1 and is affected by one of the following three instructions:
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
EXTERNAL MEMORY
The DS89C420 executes external memory cycles for code fetches and read/writes of external program and data
memory. A non-page external memory cycle is four times slower than the internal memory cycles (i.e., an external
memory cycle contains four system clocks). For this reason, although a DS89C420 can be substituted for a ROM-
less 8051 device (DS80C310, C320, etc.), there is no increase in execution speed.
However, a page mode external memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4,
or 8 system clocks for a page miss, depending on user selection. The DS89C420 also supports a second page
mode operation with a different external bus structure that provides for fast external code fetches but uses 4
system clock cycles for data memory access.
EXTERNAL PROGRAM MEMORY INTERFACE (NON-PAGE MODE)
Figure 8 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set to 10b,
assuming the microcontroller is in non-page mode for external fetches. Note that an external program fetch takes 4
system clocks, and an internal program fetch requires only 1 system clock.
As illustrated in Figure 8, ALE is deasserted when executing an internal memory fetch. The DS89C420 provides a
programmable user option to turn on ALE during internal program memory operation. ALE is automatically enabled
for code fetch externally, independent of the setting of this option.
PSEN is only asserted for external code fetches, and is inactive during internal execution.
EXTERNAL DATA MEMORY INTERFACE IN NON-PAGE MODE OPERATION
Just like the program memory cycle, the external data memory cycle is four times slower than the internal data
memory cycle in non-page mode. A basic internal memory cycle contains one system clock and a basic external
memory cycle contains four system clocks for non-page mode operation.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus
cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. Software can change the
stretch value dynamically by changing the setting of CKCON.2–CKCON.0. Table 5 shows the data memory cycle
stretch values and their effects on the external MOVX-memory bus cycle and the control signal pulse width in terms
of the number of oscillator clocks. A stretch machine cycle always contains four system clocks.
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