DS89C420_05 Datasheet, PDF (40/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
OSCILLATOR-FAIL DETECT
The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal
oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the
OFDE (PCON.4) bit to logic 1 enables the circuit. The OFDE bit is only cleared from logic 1 to logic 0 by a power-
fail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to logic 1. This flag is
cleared by software or power-on reset. Note that this circuit does not force a reset when the oscillator is stopped by
the software-enabled stop mode.
POWER MANAGEMENT MODE
Power management mode offers a software-controllable power-saving scheme by providing a reduced instruction
cycle speed, which allows the DS89C420 to continue to operate while using an internally divided version of the
clock source to save power. Power management mode is invoked by software setting the clock-divide control bits
CD1 and CD0 (PMR.7-6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for 1 machine cycle. On
all forms of reset, the clock-divide control bits default to 10b, which selects 1 oscillator cycle per machine cycle.
Since the clock speed choice affects all functional logic including timers, the DS89C420 implements several
hardware switchback features that allow the clock speed to automatically return to the divide-by-1 mode from a
reduced cycle rate. Setting the SWB (PMR.5) bit to a 1 in software enables this switchback function.
When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the system
forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an
externally enabled (and allowed through nesting priorities) interrupt. The switchback occurs whenever one of the
two conditions occur. The first switchback condition is initiated by the detection of a low on either INT0, INT1, INT3
or INT5, or a high on INT2 or INT4 when the respective pin has been programmed and allowed (through nesting
priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to
receive data and is found to have an active-low transition on the respective receive input pin. Serial port transmit
activity also forces a switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is
independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024
mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by-
1 mode. Note also that the switchback interrupt relationship requires that the respective external interrupt source is
allowed to actually generate an interrupt as defined by the priority of the interrupt and the state of the nested
interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting
of serial port enable. Disabling external interrupts and serial port receive/transmission mode disable the automatic
switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of
the clock divider are disabled. All other clock modes ignore the switchback relationship and are unaffected by
interrupts and serial port activity.
The basic divide-by-12 mode for the timers (TxMH, TxM = 00b), as well as the divide-by-32 and 64 for mode 2 on
the serial ports, are maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. Serial
ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and
require the switchback function to automatically return to the divide-by-1 mode for proper operation when a
qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation.
It is possible to enable a receive function on a serial port when incoming data is not present and then change to the
higher divide ratio. An inactive serial port receive/transmit mode requires the receive input pin to remain high and
all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the clock-
divide control bits from a divide-by-1 to a 1024 divide ratio. In the case when the serial port is being used to receive
or transmit data it is very important to validate an attempted change in the clock-divide control bits (read CD1 and
CD0 to verify write was allowed) before proceeding with low-power program functions.
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