DS89C420_05 Datasheet, PDF (32/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 10)
MD2:MD0
000
001
010
011
100
101
110
111
STRETCH
CYCLES
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12,288
4
8
16
16,384
5
10
20
20,480
6
12
24
24,576
7
14
28
28,672
Table 10. Page Mode 2, Data Memory Cycle Stretch Values (Pages1:Pages0 = 11)
MD2:MD0
000
001
010
011
100
101
110
111
STRETCH
CYCLES
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12,288
4
8
16
16,384
5
10
20
20,480
6
12
24
24,576
7
14
28
28,672
As shown in the previous tables, the stretch feature supports eight stretched external data-memory access cycles
that can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on
external data-memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch
value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles,
respectively. Note that the first stretch value does not result in adding four system clocks to the control signals. This
is because the first stretch uses one system clock to create additional address setup and data bus float time, and
one system clock to create additional address and data hold time. When using very slow RAM and peripherals, a
larger stretch value (4–7) can be selected. In this stretch category, two stretch cycles are used to create additional
setup (the ALE pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to
create additional hold time. The following timing diagrams illustrate the external data-memory access at divide-by-1
system clock mode (CD1:CD0 = 10b).
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