DS89C420_05 Datasheet, PDF (21/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification.
The same precaution should be applied if the internal program memory size is modified while executing from
external program memory.
For non-page mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and
the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is
logic 0. EA overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable
when port 0 and port 2 fetch from external program memory.
The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX
instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the
address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers
to move data over the entire 64kB external data memory space. Software selects the data pointer to be used by
writing to the SEL bit (DPS.0).
The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external
memory interface into page mode operation.
Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that
of internal operations. This is due to the CPU being stalled for three out of four clocks waiting for the data fetch,
which takes four clocks. Page Mode 1 is the only external addressing mode where the CPU does not require stalls
for external memory access, but page misses result in reduced external access performance.
ON-CHIP PROGRAM MEMORY
The processor can fetch the full on-chip program memory range automatically. The reset routines and all interrupt
vectors are located in the lower 128 bytes of the on-chip program memory area.
On-chip program memory is logically divided into two 8kB flash memory banks and is designed to be programmed
with the standard 5V V_CC supply by using a built-in program memory loader. It can also be programmed in standard
flash or EPROM programmers. The DS89C420 incorporates a memory management unit (MMU) and other
hardware to support any of the two programming methods. The MMU controls program and data memory access,
and provides sequencing and timing controls for programming the on-chip program memory. There is also a
separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and
other flash options.
SECURITY FEATURES
The DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing
the data in encrypted form. The encryption array is implemented in a security flash memory block that has the
same electrical and timing characteristics as the on-chip program memory. Once the encryption array is
programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data is XNORed with a
byte in the encryption array during verification.
A three-level lock restricts viewing of the internal program and data memory contents. By programming the three
lock bits, the user can select a level of security as specified in Table 3. Once a security level is selected and
programmed, the setting of the lock bits remains. Only a mass erase can erase these bits to allow reprogramming
the security level to a less restricted protection.
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