DS89C420_05 Datasheet, PDF (26/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Figure 8. External Program Memory Access (Non-Page Mode and CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
Ext Memory Cycle
C1 C2 C3 C4
Ext Memory Cycle
C1 C2 C3 C4
ALE
PSEN
Port 0
LSB Add
Data LSB Add
Data
Port 2
MSB Add
MSB Add
Table 5. Data Memory Cycle Stretch Values
MD2:MD0
000
001
010
011
100
101
110
111
STRETCH
CYCLES
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12288
4
8
16
16384
5
10
20
20480
6
12
24
24576
7
14
28
28672
As shown in Table 5, the stretch feature supports eight stretched external data-memory access cycles that can be
categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on external data
memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch value is set to
1, 2, or 3, the external data-memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. Note
that the first stretch value does not result in adding four system clocks to the RD/WR control signals. This is
because the first stretch uses one system clock to create additional setup time and one system clock to create
additional address hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be
selected. In this stretch category, one stretch machine cycle (4 system clocks) is used to stretch the ALE pulse
width, one stretch machine cycle is used to create additional setup, one stretch machine cycle is used to create
additional hold time, and one stretch machine cycle is added to the RD or WR strobes.
Figure 9 and Figure 10 illustrate the timing relationship for external data-memory access in full speed
(stretch value = 0), in the default stretch setting (stretch value = 1), and slow data-memory accessing
(stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).
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