DS89C420_05 Datasheet, PDF (24/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Table 4. Parallel Programming Instruction Set
INSTRUCTION
P2.5:0,
P1.7:0
P0.7:0 PROG P2.6 P2.7
Mass Erase
Don’t care Don’t care PL⁽¹⁾ H
L
Write Program
Memory
Read Program
Memory
Write Encryption
Array
ADDR
ADDR
ADDR
DIN
DOUT
DIN
PL⁽³⁾
L
H
H⁽⁴⁾
L
L
PL⁽³⁾
L
H
Write LB1
Don’t care Don’t care PL⁽³⁾ H
H
P3.6
L
H
H
L
H
P3.7
L
H
H
H
H
OPERATION
Mass erase the 16k x 8 program
memory, the security block and the bank
select. The contents of every memory
location is returned to FFh.
Program the 16k program memory.
Verify the 16k program memory.
Program the 64 byte encryption array.
Program LB1 to logic 0.
Write LB2
Don’t care Don’t care PL⁽³⁾ H
H
L
L Program LB2 and LB1 to 00b.
Write LB3
Don’t care Don’t care PL⁽³⁾ H
L
H
L Program LB3, LB2, and LB1 to 000b.
Verify the lock bits. The lock bits are at
Read Lock Bits Don’t care
DOUT
H⁽⁴⁾
L
L
L
H
address 40h and the three LSBs of the
DOUT are the logic value of the lock bits
LB3, LB2, and LB1, respectively.
Write Option
Control Register
Don’t care
DIN
Program the option control register. Bit 3
PL⁽³⁾
L
H
L
L of the DIN represents the watchdog
POR default setting.
Erase Option
Control Register
Don’t care
Don’t care PL⁽²⁾
H
L
L
Erase the option control register. This
H operation disables the watch-dog reset
function on power-up.
30h = Manufacturer ID
31h = Device ID
Read Address 30,
31, 60, FC
ADDR
DOUT
H⁽⁴⁾
L
L
L
L
60h = Device extension
FCh = Verify the option control register.
Bit 3 of the DOUT is the logic value of
the watchdog POR.
1) _{Mass erase requires an active-low PROG pulse width of 828ms.}
2) _{Erase option control register requires an active-low PROG pulse width of 828ms.}
3) _{Byte program requires an active-low PROG pulse width of 100ms max.}
4) _{PROG is weakly pulled to a high internally.}
Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready.
Note 2: P3.0 is pulled high during programming to indicate an error.
DATA POINTER INCREMENT/DECREMENT AND OPTIONS
The DS89C420 incorporates a hardware feature to assist applications that require data pointer
increment/decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how the INC
DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). Setting ID0 = 1 and SEL = 0
enables the decrement operation for DPTR, and execution of the INC DPTR instruction decrements the DPTR
contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the decrement operation for DPTR1, and execution of
the INC DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data
pointers to operate in four ways for the INC DPTR instruction:
ID1
ID0
SEL = 0
SEL = 1
0
0
Increment DPTR
Increment DPTR1
0
1
Decrement DPTR
Increment DPTR1
1
0
Increment DPTR
Decrement DPTR1
1
1
Decrement DPTR
Decrement DPTR1
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