MAX14830_15 Datasheet, PDF (63/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX14830 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and keep it low during the high period of the
ninth clock pulse (Figure 26). To generate a NACK, leave
SDA high before the rising edge of the ninth clock pulse
and keep it high for the duration of the ninth clock pulse.
Monitoring for NACK bits allows for detection of unsuc-
cessful data transfers.
Applications Information
Startup and Initialization
The MAX14830 is initialized following power-up or a
hardware or software reset (Figure 27). Check that the
MAX14830 is ready for operation after a power-up or
reset by monitoring the IRQ output, if interrupt driven
operation is employed.
In polled mode, repeatedly read a known register until the
expected contents are returned.
Low-Power Operation
To reduce the power consumption during normal opera-
tion, the following techniques can be adopted:
• Do not use the internal PLL. This saves the most
power of the options listed here. Disable and bypass
the PLL.
• When any of the four UARTs are not being used, sop
clicking via CLKDisabl.
• Use an external 1.8V supply at V₁₈. This saves the
power dissipated in the internal 1.8V linear regulator
for the 1.8V core supply. Disable the internal regulator
by connecting LDOEN to DGND.
• Keep internal clock rates as low as possible.
• Use a low voltage on the V_A supply.
Interrupts and Polling
Monitor the MAX14830 by polling the ISR register or by
monitoring the IRQ output. In polled mode, the IRQ physi-
cal interrupt output is not used and the host controller
polls the ISR register at frequent intervals to establish the
state of the MAX14830.
Alternatively, the physical interrupt, IRQ, of the MAX14830
can be used to interrupt the host controller at specified
events, making polling unnecessary. The IRQ output is
an open-drain output that requires a pullup resistor to V_L.
S
SCL
SDA
1
2
8
9
NOT ACKNOWLEDGE
ACKNOWLEDGE
Figure 26. Acknowledge Bits
POWER-UP/RST
INPUT PULLED HIGH
ENABLE
INTERRUPTS
IRQ IS HIGH?
OR
DIVLSB READ
NO
SUCCESSFULLY?
YES
CONFIGURE
CLOCKING
CONFIGURE
FIFO CONTROL
CONFIGURE
FLOW CONTROL
CONFIGURE
GPIOs
CONFIGURE
MODES
START
COMMUNICATION
Figure 27. Startup and Initialization Flow Chart
Logic-Level Translation
The MAX14830 can be directly connected to transceivers
and controllers that have different supply voltages. The
V_L input defines the logic voltage levels of the controller
interface while the V_EXT voltage defines the logic of the
transceiver interface. This ensures flexibility when select-
ing a controller and transceiver. Figure 28 is an example
of a setup when the controller, transceiver, and the
MAX14830 are powered by three different supplies.
IO-Link Application
The Typical Operating Circuit shows a four-part IO-link
master circuit with SPI control on the MAX14830 and the
IO-link transceivers.
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