MAX14830_15 Datasheet, PDF (29/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Register Map (continued)
REGISTER
ADDR
BIT7
GPIOs
GPIOConfg¥
GPIOData¥
0x18
0x19
GP3OD
GPI3Dat
CLOCK CONFIGURATION
PLLConfig*^‡
0x1A
PLLFactor1
BRGConfig
0x1B
—
DIVLSB
0x1C
Div7
DIVMSB
CLKSource*‡
0x1D
0x1E
Div15
CLKtoRTS
GLOBAL REGISTERS
GlobalRQ
0x1F
0
GloblComnd
0x1F
GlbCom7
SYNCHRONIZATION REGISTERS
TxSynch#
0x20
CLKtoGPIO
SynchDelay1#
0x21
SDelay7
SynchDelay2#
0x22
SDelay15
TIMER REGISTERS
TIMER1#
0x23
TIMER2#
0x24
Timer7
TmrToGPIO
REVISION
REVID*†#
0x25
1
BIT6
GP2OD
GPI2Dat
PLLFactor0
CLKDisabl
Div6
Div14
—
0
GlbCom6
TxAutoDis
SDelay6
SDelay14
Timer6
Timer14
0
BIT5
GP1OD
GPI1Dat
PreDiv5
4xMode
Div5
Div13
—
0
GlbCom5
TrigDelay
SDelay5
SDelay13
Timer5
Timer13
1
BIT4
BIT3
BIT2
GP0OD
GPI0Dat
GP3Out
GPO3Dat
GP2Out
GPO2Dat
PreDiv4
2xMode
Div4
Div12
—
PreDiv3
FRACT3
Div3
Div11
PLLBypass
PreDiv2
FRACT2
Div2
Div10
PLLEn
0
GlbCom4
IRQ3
GlbCom3
IRQ2
GlbCom2
SynchEn
SDelay4
SDelay12
TrigSel3
SDelay3
SDelay11
TrigSel2
SDelay2
SDelay10
Timer4
Timer12
Timer3
Timer11
Timer2
Timer10
1
0
0
BIT1
GP1Out
GPO1Dat
PreDiv1
FRACT1
Div1
Div9
CystalEn
IRQ1
GlbCom1
TrigSel1
SDelay1
SDelay9
Timer1
Timer9
1
BIT0
GP0Out
GPO0Dat
PreDiv0
FRACT0
Div0
Div8
—
IRQ0
GlbCom0
TrigSel0
SDelay0
SDelay8
Timer0
Timer8
1
*Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x08, REVID = 0xB1.
†Denotes nonread/write value: RHR = R, THR = W, ISR = COR, SpclCharInt = COR, STSInt = R/COR,
LSR = R, TxFIFOLvl = R, RxFIFOLvl = R, REVID = R.
¥Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7, UART2:
GPIO8–GPIO11, UART3: GPIO12–GPIO15.
‡This register can only be programmed by accessing UART0.
#This register can only be directly addressed in I²C mode. Use extended addressing when operating in SPI mode.
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