MAX14830_15 Datasheet, PDF (51/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
PLLConfig—PLL Configuration Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
PLLFactor1
0
0x1A
R/W
6
PLLFactor0
0
5
PreDiv5
0
4
PreDiv4
0
3
PreDiv3
0
2
PreDiv2
0
1
PreDiv1
0
0
PreDiv0
1
The PLLFactor[n] bits allow programming the PLL multiplication factors. The input and output frequencies of the PLL have
to be limited to the ranges shown in Table 7. Enable the PLL through CLKSource[2].
Bits 5–0: PreDiv[n]
The PreDiv[n] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen so that the output
frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4. The input
frequency of XIN, is f_CLK:
f_PLLIN = f_CLK/PreDiv
See Figure 17. PreDiv is an integer that must be in the range of 1 to 63.
Bit 7: No Function
fCLK
fPLL IN
PRE-DIVIDER
f_REF
FRACTIONAL
PLL
BAUD-RATE
GENERATORS
Figure 17. PLL Signal Path
Table 7. PLLFactor_ Selector Guide
PLLFactor1
0
0
1
1
PLLFactor0
0
1
0
1
MULTIPLICATION FACTOR
6
48
96
144
f_PLLIN
MIN
MAX
500kHz
800kHz
850kHz
1.2MHz
425kHz
1MHz
390kHz
667kHz
f_REF
MIN
MAX
3MHz
4.8MHz
40.8MHz
56MHz
40.8MHz
96MHz
56MHz
96MHz
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