MAX14830_15 Datasheet, PDF (57/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
TIMER2—Timer Register 2
ADDRESS:
MODE:
BIT
7
NAME TmrToGPIO
RESET
0
0x24
R/W
6
Timer14
0
5
Timer13
0
4
Timer12
0
3
Timer11
0
2
Timer10
0
1
Timer9
0
0
Timer8
0
The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output.
The low-frequency clock is a divided replica of the fractional divider output.
Bit 7: TmrToGPIO
Set TmrToGPIO to 1 to enable clock generation at a GPIO output. The clock signal is routed to a GPIO output as
follows: UART0 clock signal to GPIO1, UART1 clock signal to GPIO5, UART2 clock signal to GPIO9, UART3 clock signal
to GPIO13. The output clock has a 50% duty cycle.
Bits 6–0: Timer[n]
Timer[14:8] are the 7 MSBs of the 15-bit timer divisor. The clock frequency is calculated using the following formula:
f_{TIMER_CLK} = UARTClk/(1024 x Timerx)
where UARTClk is the fractional baud-rate generator output (i.e. 16 x BaudRate). When using 2x or 4x rate modes,
UARTClk is 8 x BaudRate or 4 x BaudRate, respectively.
If TIMER1 and TIMER2 are both 0x00, the low-frequency clock is off.
RevID—Revision Identification Register
ADDRESS:
0x25
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESET
1
0
1
1
0
0
1
1
Bits 7–0: Bit[n]
The RevID register indicates the revision number of the MAX14830 silicon—starting with 0xB1. This can be used during
software development as a known reference.
www.maximintegrated.com
Maxim Integrated │  57