MAX14830_15 Datasheet, PDF (19/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
RECEIVED DATA
MID BIT
SAMPLING
LSB
START
D0
D1
D2
D3
D4
MSB
D5
D6
D7
PARITY
STOP STOP
Figure 4. Receive Data Format
RECEIVER
RECEIVED
DATA
RX_
OVERRUN
LSR[1]
WORD
ERROR 128
TRIGGER
ISR[3]
FIFOTrgLvl[7:4]
RECEIVE FIFO
CURRENT FILL LEVEL
RxFIFOLvl
I²C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
TIMEOUT
EMPTY
ERRORS
Figure 5. Receive FIFO
4
3
2
RHR
1
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst. To halt transmis-
sion, set MODE1[1]: TxDisabl to 1. After MODE1[1] is
set, the transmitter completes transmission of the current
character and then ceases transmission.
The TX_ output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes that IrDA[5] is 0.
Note: Errors in transmitted data can occur when the THR
is being written to while the transmitter is sending data.
See the THR register description for details.
Receiver Operation
The receiver expects the format of the data at RX_ to be
as shown in Figure 4. The quiescent logic state is high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are deposited
into the Receive FIFO. Errors and status information are
stored for every received word (Figure 5). The host reads
the data out of the Receive FIFO through the Receive
Hold Register (RHR), oldest data first. The status information
of the most recently read word in the RHR is located in
the Line Status Register (LSR). After a word is read out
of the RHR, the LSR contains the status information for
that word. Note: If data is read out of RHR simultaneously
when the receiver is receiving data, errors can occur. See
the RHR register description for details.
RX_
A
ONE BIT PERIOD
BAUD
BLOCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MAJORITY
CENTER
SAMPLER
Figure 6. Midbit Sampling
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