MAX14830_15 Datasheet, PDF (35/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Bit 0: RTimeout
The RTimeout bit indicates that stale data is present in the Receive FIFO. RTimeout is set when the youngest character
resides in the RxFIFO for a period longer than the time programmed into the RxTimeOut register. The timeout counter
restarts when at least one character is read out of the RxFIFO or a new character is received by the RxFIFO. If the value
in RxTimeOut is zero, LSR[0]: RTimeout is disabled. The RTimeout flag can generate an ISR[0] interrupt, if enabled
through LSRIntEn[0].
SpclChrIntEn—Special Character Interrupt Enable Register
ADDRESS:
MODE:
BIT
7
NAME
—
RESET
0
0x05
R/W
6
—
0
5
MltDrpIntEn
0
4
BREAKIntEn
0
3
XOFF2IntEn
0
2
XOFF1IntEn
0
1
XON2IntEn
0
0
XON1IntEn
0
Bits 7, 6: No Function
Bit 5: MltDrpIntEn
The MltDrpIntEn bit enables routing the SpclCharInt[5]: MultiDropInt interrupt to ISR[1]. If MltDrpIntEn is set low (default),
the MultiDropInt is not routed to the ISR[1].
Bit 4: BREAKIntEn
The BREAKIntEn bit enables routing the SpclCharInt[4]: BREAKInt interrupt to ISR[1]. If BREAKIntEn is set low (default),
the BREAKInt is not routed to the ISR[1].
Bit 3: XOFF2IntEn
The XOFF2IntEn bit enables routing the SpclCharInt[3]: XOFF2Int interrupt to ISR[1]. If XOFF2IntEn is set low (default),
the XOFF2Int is not routed to the ISR[1].
Bit 2: XOFF1IntEn
The XOFF1IntEn bit enables routing the SpclCharInt[2]: XOFF1Int interrupt to ISR[1]. If XOFF1IntEn is set low (default),
the XOFF1Int is not routed to the ISR[1].
Bit 1: XON2IntEn
The XON2IntEn bit enables routing the SpclCharInt[1]: XON2Int interrupt to ISR[1]. If XON2IntEn is set low (default), the
XON2Int is not routed to the ISR[1].
Bit 0: XON1IntEn
The XON1IntEn bit enables routing the SpclCharInt[0]: XON1Int interrupt to ISR[1]. If XON1IntEn is set low (default), the
XON1Int is not routed to the ISR[1].
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