MAX14830_15 Datasheet, PDF (31/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
IRQEn—IRQ Enable Register
ADDRESS:
MODE:
BIT
7
NAME CTSIEn
RESET
0
0x01
R/W
6
RFifoEmtyIEn
0
5
TFifoEmtyIEn
0
4
TFifoTrgIEn
0
3
RFifoTrgIEn
0
2
STSIEn
0
1
SpclChrIEn
0
0
LSRErrIEn
0
The IRQEn register is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled
to generate an IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or
behavior. Every one of the IRQEn bits operates on an ISR bit.
Note that an error can occur in the TxFIFO when a character is written into THR at the same time as the transmitter is
transmitting out data via TX. In the event of this error condition, the result is that a character will not be transmitted.
In order to avoid this, stop the transmitter when writing data to the THR. This can be done via the TxDisable bit in the
MODE1 register.
Bit 7: CTSIEn
The CTSIEn bit enables IRQ interrupt generation when the CTSInt interrupt bit is set in the ISR. Set the CTSIEn bit low
to disable IRQ generation from CTSInt.
Bit 6: RFifoEmtyIEn
The RFifoEmtyIEn bit enables IRQ interrupt generation when the RFifoEmptyInt interrupt bit is set in the ISR. Set the
RFifoEmtyIEn bit low to disable IRQ generation from RFifoEmptyInt.
Bit 5: TFifoEmtyIEn
The TFifoEmtyIEn bit enables IRQ interrupt generation when the TFifoEmptyInt interrupt bit is set in the ISR. Set the
TFifoEmtyIEn bit low to disable IRQ generation from TFifoEmptyInt.
Bit 4: TFifoTrgIEn
The TFifoTrgIEn bit enables IRQ interrupt generation when the TFifoTrigInt interrupt bit is set in the ISR. Set TFifoTrgIEn
bit low to disable IRQ generation from TFifoTrigInt.
Bit 3: RFifoTrgIEn
The RFifoTrgIEn bit enables IRQ interrupt generation when the RFifoTrigInt interrupt bit is set in the ISR. Set the
RFifoTrgIEn bit low to disable IRQ generation from RFifoTrigInt.
Bit 2: STSIEn
The STSIEn bit enables IRQ interrupt generation when the STSInt interrupt bit is set in the ISR. Set the STSIEn bit low
to disable IRQ generation from STSInt.
Bit 1: SpclChrIEn
The SpclChrIEn bit enables IRQ interrupt generation when the SpCharInt interrupt bit is set in the ISR. Set the SpclChrIEn
bit low to disable IRQ generation from SpCharInt.
Bit 0: LSRErrIEn
The LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set the
LSRErrIEn low to disable IRQ generation from LSRErrInt.
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