MAX14830_15 Datasheet, PDF (41/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Bit 0: RST
Set the RST bit high to reset the selected UART in the MAX14830. The SPI/I²C bus stays active during this reset and
communication with the MAX14830 is possible. All register bits in the selected UART are reset to their reset state and
the FIFOs are cleared during a reset.
The global registers are not reset when the RST bit for a given UART is set. Once set high, the RST bit must be cleared
by writing a 0 to RST.
LCR—Line Control Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
RTSbit
0
0x0B
R/W
6
TxBreak
0
5
ForceParity
0
4
EvenParity
0
3
ParityEn
0
2
StopBits
1
1
Length1
0
0
Length0
1
Bit 7: RTSbit
The RTSbit provides direct control of the RTS_ output logic. If RTSbit is set to 1, then RTS_ is set to logic-high. The
RTSbit only works when CLKSource[7]: CLKtoRTS is set to 0.
Bit 6: TxBreak
Set TxBreak to 1 to generate a line break whereby the TX_ output is held low. TX_ output remains low until TxBreak is
set to 0.
Bit 5: ForceParity
The ForceParity bit enables forced parity, as used in 9-bit multidrop communication. Set both LCR[3]: ParityEn and
ForceParity to 1 to use forced parity. The parity bit is forced high by the transmitter if LCR[4]: EvenParity is low. The parity
bit is forced low if the EvenParity bit is high.
Bit 4: EvenParity
Set the EvenParity bit to 1 to generate even parity by the transmitter and parity is checked by the receiver. Odd parity
generation and checking are used if EvenParity is set low.
Bit 3: ParityEn
The ParityEn bit enables the use of a parity bit on the TX_ and RX_ interfaces. Set the ParityEn bit to 0 to disable parity
usage.
When the ParityEn bit is 1, the transmitter generates the parity bit as defined in LCR[4], and the receiver checks the
parity bit.
Bit 2: StopBits
This defines the number of STOP bits and depends on the length of the word programmed in LCR[1:0] (Table 2). When
LCR[2] is high and the word length is 5, the transmitter generates a word with a STOP bit length equal to 1.5. Under
these conditions, the receiver recognizes a STOP bit length greater than a 1-bit duration.
Bits 1, 0: Length[n]
The Length[n] bits configure the length of the words that the transmitter generates and the receiver checks for at the
asynchronous TX_ and RX_ interfaces (Table 3).
Table 2. StopBits Truth Table
Table 3. Length_ Truth Table
StopBits
BIT
0
1
1
WORD LENGTH
5, 6, 7, 8
5
6, 7, 8
STOP BIT LENGTH
1
1–1.5
2
Length1
0
0
1
1
Length0
0
1
0
1
WORD LENGTH
5
6
7
8
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