MAX14830_15 Datasheet, PDF (53/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
CLKSource—Clock Source Register
ADDRESS:
0x1E
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME CLKtoRTS
—
—
—
PLLBypass
PLLEn
CrystalEn
—
RESET
0
0
0
0
1
0
0
0
Bit 7: CLKtoRTS
Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS_. The clock frequency
is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
Bits 6, 5: No Function
Bit 4:
Bi 4 can be programmed to logic 0 or logic 1.
Bit 3: PLLBypass
Set the PLLBypass bit to 1 to enable bypassing the internal PLL and predivider.
Bit 2: PLLEn
Set the PLLEn bit to 1 to enable the internal PLL. Set PLLEn to 0 to disable the internal PLL.
Bit 1: CrystalEn
Set the CrystalEn bit to 1 to enable the crystal oscillator. When using an external clock source at XIN, set CrystalEn to 0.
Bit 0:
Always keep Bit 0 at logic 0.
GlobalIRQ—Global IRQ Register
ADDRESS:
0x1F
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
—
IRQ3
IRQ2
IRQ1
IRQ0
RESET
0
0
0
0
1
1
1
1
Bits 7–4: No Function
Bits 3–0: IRQ[n]
The MAX14830 has a single IRQ output. The GlobalIRQ register bits report which of the UARTs have an interrupt pend-
ing, as enabled in the ISRIntEn registers.
The GlobalIRQ register can be read in two ways: either by reading register 0x1F of any of the four UARTs or by sampling
the 4 bits sent to the master on MISO during the command byte of a read cycle (full-duplex SPI) (see the Fast Read
Cycle section for more information).
IRQ[n] is set to 0 when the associated UART’s internal IRQ is generated.
IRQ_ bits are cleared when the associated UART interrupt is cleared. UART interrupts are cleared by reading the UART
ISR register.
www.maximintegrated.com
Maxim Integrated │  53