MAX14830_15 Datasheet, PDF (54/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
GloblComnd—Global Command Register
ADDRESS:
MODE:
BIT
7
NAME GlbCom7
0x1F
W
6
GlbCom6
5
GlbCom5
4
GlbCom4
3
GlbCom3
2
GlbCom2
1
GlbCom1
0
GlbCom0
Bits 7–0: GlbCom[n]
The GloblComnd register is the only global write register in the MAX14830. Every byte written to GloblComnd is sent
simultaneously to all four UARTs. Every byte sent by the SPI/I²C master to location 0x1F is interpreted as a global
command by all the four internal UARTs.
The MAX14830 logic supports the following commands (Table 8):
• Global Tx Synchronization
• Extended Addressing Space Enable (to get access to registers beyond address 0x1F)
• Extended Addressing Space Disable (to disable access to registers beyond address 0x1F)
The last two commands (0xCE/0xCD) enable/disable the access to registers in the extended space of the register map
when MAX14830 operates in SPI mode. The SPI command byte has only 5 bits to address a given register so that the
registers beyond 0x1F could not be addressed using the standard access method.
In I²C mode, there is no need to explicitly enable and disable the extended register map access as I²C allows up to 7
bits for register addressing.
To extend the addressing capability of the SPI command byte, send a 0xCE to location 0x1F. The internal SPI address
is generated as 0010 A3A2A1A0, where A3A2A1A0 is the least significant nibble of the command byte. Bit A4 of the
command byte is disregarded when the extended space of the register map is enabled and only the least significant
nibble is used for addressing purposes (Table 9).
Bits U1 and U0 of the command byte maintain their meaning in the extended mode. See the SPI Interface section for
more information.
To return to standard addressing mode, the SPI master has to send the 0xCD command. In this case, the internal SPI
address is generated as follows (default): 000A4 A3A2A1A0
Table 8. GloblComnd Command Descriptions
GloblComnd[7:0]
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
COMMAND DESCRIPTION
Tx Command 0
Tx Command 1
Tx Command 2
Tx Command 3
Tx Command 4
Tx Command 5
Tx Command 6
Tx Command 7
Tx Command 8
Tx Command 9
Tx Command 10
Tx Command 11
Tx Command 12
Tx Command 13
Tx Command 14
GloblComnd[7:0]
0xEF
0xCE
0xCD
COMMAND DESCRIPTION
Tx Command 15
Enable extended register map access
Disable extended register map access
Table 9. Extended Mode Addressing
(SPI only)
REGISTER
TxSynch
SynchDelay1
SynchDelay2
TIMER1
TIMER2
RevID
SPI MODE
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
I²C MODE
ADDRESS
0x20
0x21
0x22
0x23
0x24
0x25
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