MAX14830_15 Datasheet, PDF (30/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Detailed Register Descriptions
The MAX14830 has registers that are 8 bits wide.
RHR—Receive Hold Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
RData7
X
0x00
R
6
RData6
X
5
RData5
X
4
RData4
X
3
RData3
X
2
RData2
X
1
RData1
X
0
RData0
X
Bits 7–0: RData[n]
The RHR is the bottom of the Receive FIFO and is the register used for reading data out of the Receive FIFO. It contains
the oldest (first received) character in the Receive FIFO. RHR[0] is the first data bit of the serial-data word received by
the receiver at the RX pin.
Note that the the data read out of RHR can be in error. This occurs when the UART receiver is receiving a character at
the same time as a value is being read out of RHR and the FIFO level counter is being updated. In the event of this error
condition, the result is that a character is read out twice from the RHR. To avoid this, the receiver should not be receiving
data while the RHR is being read out. This can be achieved via flow control, or prior knowledge of the amount of data
that is expected to be received.
THR—Transmit Hold Register
ADDRESS:
MODE:
BIT
NAME
7
TData7
0x00
W
6
TData6
5
TData5
4
TData4
3
TData3
2
TData 2
1
TData1
0
TData0
Bits 7–0: TData[n]
The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited
in the Transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right
after the START bit.
Note that an error can occur in the TxFIFO when a character is written into THR at the same time as the transmitter
is transmitting out data via TX. In the event of this error condition, the result is that a character will not be transmitted.
To avoid this, stop the transmitter when writing data to the THR. This can be done via the TxDisable bit in the MODE1
register.
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