M08035 Datasheet, PDF (46/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Control Registers Map and Descriptions
Register Address: 16h
Default:
20h
Register Name: Reclocker BW Control
Description:
Controls bandwidth of Reclocker
Bit
7 Reserved
6:4 000b: Reserved (do not use)
001b: 0.5 x Nominal LBW
010b: 1 x Nominal LBW
011b: 4 x Nominal LBW
100b: 2 x Nominal LBW
101b: 3 x Nominal LBW
110b: 1.5 x Nominal LBW
111b: 0.875 x Nominal LBW
3:0 Reserved
Bit Description
Register Address: 18h
Default:
00h
Register Name: SD/xHD Algorithm Control
Description:
Controls SD/xHD output of Reclocker
Bit
Bit Description
7:6 Reserved
5 0b: SD/xHD output conforms to case 1, Table 4-11
1b SD/xHD output conforms to case 2, Table 4-11
4:0 Reserved
5.1.3
Checksum for Memory Interface Configuration
Register Address: 1Ah
Default:
55h
Register Name: Checksum
Description:
Checksum value to be added to sum of reg 00h to 19h contents
Bit
Bit Description
7:0 Checksum value
5.1.4
Status/Monitoring
Register Address: 80h
Default:
00h
Register Name: Reset
Description:
Does Master Reset on Device
Bit
Bit Description
7:0 00h: Normal Operation
AAh: Master Reset
M08035, M08045 Data Sheet V1
080x5-DSH-001
MACOM™
Default
R/W
0b
R/W
010b
R/W
0000b
R/W
Default
R/W
00b
R/W
0b
R/W
00000b
R/W
Default
R/W
01010101b
R/W
Default
R/W
00000000b
R/W
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