M08035 Datasheet, PDF (27/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
Figure 4-7. Four-Wire Sequential WRITE
SCLK
xCS
SI
SO
1 2 3 ... 11 12 13 14 ... 20 21 22 23 ... 29 30 ...
Tcs
1 R/W
Address[7:0]
Tdh
1^st Data[7:0]
Tds
2^nd Data[7:0]
3^rd Data[7:0]
On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 15 bits following SB
and OP are used. On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or
OP renders the operation undefined. The falling edge of xCS always resets the serial operation for a new Read or
Write cycle.
Detailed timing information is shown below.
Table 4-4. Four-wire Interface Timing
Timing Symbol
Description
Min
Max
Unit
Tds
Data set-up time
5
Tdh
Data hold time
5
Tcs
xCS set-up time
5
Tch
xCS hold time
5
Tfreq, write
Four-wire interface write clock frequency
—
Tfreq, read
Four-wire interface clock read frequency,
—
DV_DDIO=2.5 V or 3.3 V
Four-wire interface read clock frequency, DV_DDIO=1.8 V
—
Four-wire interface read clock frequency, DV_DDIO=1.2 V
—
T_DUTY
SCLK duty cycle
40
Tdd
Read data output delay
1
(measured with max 30 pF loading, DV_DDIO=3.3 V)
—
ns
—
ns
—
ns
—
ns
40
MHz
40
MHz
20
MHz
5
MHz
60
%
8
ns
M08035, M08045 Data Sheet V1
MACOM™
27
080x5-DSH-001