M08035 Datasheet, PDF (33/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
As an alternative to the ARD, the user may manually set the reclocker to the desired data rate by programming
bits[3:2] in register 12h to the desired values as shown in Table 4-10.
Table 4-10. Reclocker Data Rate Selection
Reg12h (Bits 3:2)
Function
00b
ARD Enabled
01b
Manual SD rate programmed
10b
Manual HD rate programmed
11b
Manual 3G rate programmed (M08045)
Please note that when configured in manual ARD mode, the reclocker is guaranteed to lock to the program data
rate. However, it may also lock to the harmonics of that program data rate as well. For example, if the reclocker is
programmed to lock to HD data, it will also try to lock to 3G data as 2.97 Gbps is exactly twice 1.485 Gbps.
When in auto-bypass mode, if the ARD cannot determine the rate of the input data stream, it will switch the
reclocker into bypass mode. This allows a data rate other than those specified to be passed through the reclocker.
The auto-bypass mode may be disabled through Register 14h.
4.7.3
Lock Detection
Several circuits monitor each reclocker for Loss of Lock. One in particular compares the recovered serial clock to
one derived from the reference clock. If the clock frequency is within ±2000 ppm of the serial data frequency, the
Loss of Lock (LOL) alarm will be set to '0'. If the clock is outside of this window, then the LOL alarm will be asserted
to '1'.
The LOL bit can be read from bit[0] in register 88h.
4.7.4
Reference Clock
The M08035/M08045 can operate from a crystal or an external reference clock, but better jitter results are obtained
with a crystal. If using an external reference clock, this should be a 27 MHz clock with a frequency accuracy of
±100 ppm or better. Reference clock jitter is important and care must be taken to supply a low jitter reference clock
to the reclocker of 1 ps RMS or less. The reference clock may either be from an external CMOS clock oscillator or
an external parallel resonance crystal. If a low jitter 27 MHz signal is already available on the board then it may be
used. Due to the higher jitter, a genlocked 27 MHz clock is likely not suitable for this device. When supplying an
external clock signal, it is recommended to use AC coupling through a 0.1 µF capacitor. Refer to Table 1-7 for
recommended input levels.
4.8
SD/xHD Output
When the reclocker is locked to the input data, the SD/xHD output indicates whether an SD or HD rate is detected.
When a 3G rate is being received, the output will indicate HD. This output is designed to be connected to the slew
rate control on a downstream cable driver.
The SD/xHD pin has two available modes as shown in Table 4-11. These are controlled by the SDALG bit, reg
18h[5], by default this is a 0 and only goes high when the reclocker is locked to a 270 Mbps input signal. This mode
sets the fast edge on the cable driver and allows for any signal in the reclockers data range to be bypassed. If the
slow edge is set, any signal above 540 Mbps would be distorted by the slow edge on the cable driver.
M08035, M08045 Data Sheet V1
MACOM™
33
080x5-DSH-001