M08035 Datasheet, PDF (26/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
Figure 4-5. Four-wire Interface Word Format
Figure 4-6 illustrates a Serial Write Mode followed by a Serial Read mode. To initiate a Write sequence, xCS goes
low before the falling edge of SCLK. On each falling edge of the clock, the 18 bits consisting of the SB = 1, OP = 0,
ADDR, and DATA, are latched into the input shift register through SI. The rising edge of xCS may occur before or
after the falling edge of SCLK for the last bit. Upon receipt of the last bit, one additional cycle of SCLK is necessary
before DATA transfers from the input shift register to the addressed register.
To initiate a read sequence, xCS goes low before the falling edge of SCLK. On each falling edge of SCLK, the 10
bits consisting of SB = 1, OP = 1, and the 8-bit ADDR are written to the serial input shift register and copied to the
serial output shift register. On the next rising edge after the address LSB, the SB and 8 bits of the DATA are shifted
out. The SB for a Read is always 1.
Figure 4-6. Four-Wire Write Followed by a Read Sequence
SCLK
xCS
SI
SO
1 2 3 ... 10 11 ... 17 18 19 20 21 22 23 ... 31 32 33 ... 41
Tcs
1W
Address[7:0]
Tdh
Tcs
Data[7:0]
Tds
Tch
Tcs
1
R
Address[7:0]
Trdd
D7 Dx D1 D0
The 4-wire interface supports multiple consecutive writes. In this case, the address header is not needed and each
additional 8 bits of data will be written into consecutive addresses. If consecutive read/write cycles are being
performed, it is not necessary to insert an extra clock cycle between read/write cycles, however one extra clock
cycle is needed after the last data bit of the last read/write cycle.
M08035, M08045 Data Sheet V1
MACOM™
26
080x5-DSH-001