M08035 Datasheet, PDF (23/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
4.4
High-Speed Output Description
There are two high-speed outputs available on the M08035/M08045. By default, only SDOA is powered up, setting
bit 2 of register 0Ch high will enable SDOB. The output signal will be a copy of SDOA. In hardware mode, SDOB is
enabled with the SDOB/SCLK_EN input pin in a floating (F) or high (H) (see Table 3-1).
A further function of this output is a serial clock source. By setting register 06h, bit 0 to high, the reclockers
recovered clock is output to the SDOB/SCLK pins. In hardware mode this function is selected by setting SDOB/
SCLK_EN high (see Table 3-1).
The M08035/M08045 feature differential current mode logic (CML) drivers with integrated 50 Ω pull ups to AV_DDO
for the output of each reclocker channel. AV_DDO may be supplied from any voltage ranging from 1.2 V to 3.3 V.
The differential, peak-to-peak, output swing for each CML driver is programmable and may be set to 600 mV_PPD,
800 mV_PPD, or 1200 mV_PPD. Please note that the 1200 mV_PPD output swing setting is only available when AV_DDO
is supplied from a voltage of 1.8 V or greater. The swing setting may be programmed by writing to register 09h for
SDOA, and register 0Bh for SDOB.
In order to improve signal integrity when used in large systems, each output also comes equipped with
programmable de-emphasis (DE) for FR4 trace. There are four settings for output de-emphasis: 0 dB (or no DE),
2 dB, 4 dB, and 6 dB. In serial control mode, the output de-emphasis level for each input may be set by
programming the desired value to register 09h for SDOA and register 0Ah for SDOB. Alternatively, in hardware
mode, the de-emphasis level for all of the outputs may be globally set through pin DE_CTRL (MF3). In hardware
mode only the three settings of 0 dB, 4 dB, and 6 dB are available.
In most video applications, it is important to avoid AC coupled data interfaces between devices wherever possible.
In addition to reducing the number of components, DC coupling will result in more system jitter margin. In order to
accommodate DC coupling with the upstream device, the AV_DDO power domain of the M08035/M08045 is
electrically independent from all other power domains therefore allowing it to be tied to the V_DD of the downstream
device. This is demonstrated in Figure 4-4 below.
Figure 4-4. M08035/M08045 AV_DDO Connected to the V_DD of the Downstream Device
M08035/M08045
AVDDO
50 Ω
1.2V – 3.3V
Downstream Device
VDD
50 Ω
If AC coupling is desired or necessary, then the capacitor should be at least 10 µF.
M08035, M08045 Data Sheet V1
MACOM™
23
080x5-DSH-001