M08035 Datasheet, PDF (25/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
4.6.1
HIC Mode
Configuring the M08035/M08045 in hardware mode avoids the complication of adding a microcontroller, but offers
limited control options. When in hardware mode, the MF (Multi Function IO) pins are configured as shown in
Table 4-2 below.
Table 4-2. MF Pin Configuration in Hardware Mode
MF
HIC Mode Pin Name
Function
MF2
IE_CTRL
Input trace equalization control for all SDI inputs
H = 6 dB Input EQ
F = 2 dB Input EQ
L = 0 dB Input EQ
MF3
DE_CTRL
Output de-emphasis (DE) control for all SDO outputs
H = 6 dB of output DE
F = 4 dB of output DE
L = 0 dB output DE
MF4
RC_BYPASS
Reclockers bypass control for all outputs
L/H = Normal operation, Reclocker not bypassed
H = Reclocker bypassed
MF5
SDO_DIS
SDO disable control for all outputs
H = SDO disabled output logic high
L/F = SDO enabled
NOTE:
In this mode, xALARM is not supported.
4.6.2
Four-wire Interface Mode (SIC4)
In this mode, a four-wire serial interface is used to program the device's internal registers, configuring the operation
of the M08035/M08045. When in SIC4 mode, MF[0:3] pins comprise the four-wire bus as shown in Table 4-3 below.
Table 4-3. MF Pin Configuration in Four-wire Interface Mode
MF
SIC4 Mode Pin Name
MF0
SCLK
MF1
SO
MF2
SI
MF3
xCS
Function
Serial clock input
Serial data output
Serial Data input
Chip Select (active low)
The interface shifts data in from the external controller on the rising edge of SCLK. The serial I/O operation is gated
by xCS. Data is shifted in to the M08035/M08045 from the Host (Master) to SI on the falling edge of SCLK, and
shifted out through SO on the rising edge of SCLK. To address a register, a 10-bit input needs to be shifted,
consisting of the first bit (Start Bit, SB = 1), the second bit (Operation Bit, OP = 1 for read, = 0 for write), and the 8-
bit address (MSB first).
M08035, M08045 Data Sheet V1
MACOM™
25
080x5-DSH-001