M08035 Datasheet, PDF (21/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
4.2
High-Speed Differential Inputs
The M08035/M08045 feature four differential inputs compatible with PCML. LVDS and LVPECL signal levels are
also accommodated. Serial data to be retimed is presented to these four inputs. Each input is terminated with a
50 Ω termination to AV_DDI. AV_DDI can be supplied from any voltage ranging from 1.2 V to 3.3 V.
In order to improve signal integrity when used in large systems, each input also comes equipped with
programmable input equalization (IE) for FR4 trace. There are four settings for input equalization: 0 dB (or no
equalization), 2 dB, 4 dB, and 6 dB. In serial control mode, the input equalization level for each input may be set by
programming the desired value to reg00h-reg03h. Alternatively, in hardware mode, the input equalization for all of
the inputs may be set globally through the IE_CTRL (MF2) pin. In hardware mode only the three settings of 0 dB,
4 dB, and 6 dB are available.
In most video applications, it is important to avoid AC coupled data interfaces between devices wherever possible.
In addition to reducing the number of components, DC coupling will result in more system jitter margin. In order to
accommodate DC coupling with the upstream device, the AV_DDI power domain of the M08035/M08045 is
electrically independent from all other power domains, allowing it to be tied to the V_DD of the upstream device. This
is demonstrated in Figure 4-2 below.
Figure 4-2. M08035/M08045 AV_DDI Connected to the V_DD of the Upstream Device
Upstream Device
VDD
50 Ω
1.2V – 3.3V
M08035/M08045
AV _DDI
50 Ω
Alternatively and under certain conditions, the M08035/M08045 allow for the inputs to be self biased eliminating
the need for an electrical connection between the supply voltages of the upstream device and the M08035/
M08045. This configuration offers the benefit of keeping the supply of the previous device and the power domain(s)
of the M08035/M08045 completely isolated, while using DC coupling. AC coupling should not be used with the self
bias interface. This self biasing scheme is demonstrated in Figure 4-3 below.
When using the M08035/M08045 in self biased mode, specific conditions must be met:
1. The self biased inputs must be DC coupled. No AC coupling is supported in self biased mode.
2. The AV_DDO of the upstream device must be 2.5 V or greater. AV_DDO levels 1.2 V and 1.8 V are not supported
in this mode.
3. The common mode of the upstream signals must be greater than 600 mV.
4. Internal voltage regulators are disabled.
5. All inputs are configured in self biased mode. Combination of self biased and non-self biased is not supported.
M08035, M08045 Data Sheet V1
MACOM™
21
080x5-DSH-001