M08035 Datasheet, PDF (32/49 Pages) M/A-COM Technology Solutions, Inc. – SD, HD, 3G Multi-rate Reclocker

Functional Description
4.7
Reclocker Operation
4.7.1
Clock Recovery
This block generates a serial clock signal at a frequency close to the data rate. The clock signal is generated by a
phased locked loop (PLL) which uses the 27 MHz input clock as a reference.
The presence of the reference clock is monitored by the device. An alarm bit (NOREF) in register 88h is set to '1'
when a suitable reference clock is not present. Once the PLL has locked to the reference clock, the REFLOL bit in
the same register will be set to '0'. A value of '1' in this bit indicates that the PLL has not locked to the input
reference clock.
The frequency locked clock signal is supplied to the phase lock block. In this block, a bang-bang phase comparator
is used to make fine adjustments to the phase and frequency of the clock, aligning it with the incoming serial data.
Once the clock signal is phase and frequency aligned with the serial data stream, it is used to re-time the data,
producing a clean data signal that is provided at the output of the device. The phase lock block uses an integrated,
programmable loop filter. The bandwidth of the phase lock block may be programmed using the BW[2:0] bits in
register 16h. A wide bandwidth increases the jitter tolerance and reduces the lock time of the loop. However, a wide
bandwidth also allows more jitter from the input serial data stream to be transferred to the output. Alternatively, a
low bandwidth setting causes the loop to reject more of the incoming data stream's jitter, while increasing lock time,
and reducing input jitter tolerance. The bandwidth setting can be optimized for each system.
Furthermore, since the phase lock block uses a non-linear, bang-bang loop, the bandwidth of the system is
inversely proportional to the incoming data stream's jitter. This offers several advantages over linear PLLs. It
achieves higher jitter attenuation with large input jitter, while it corrects for small variations quickly with low input
jitter. With higher input jitter, the loop automatically reduces the bandwidth, causing more of the jitter to be rejected.
Conversely, a data stream with lower jitter will cause the loop bandwidth to be widened. Note that bandwidth
settings greater than 2x will increase output jitter.
When the recovered serial clock output is enabled, the clock alignment to the SDOA data output will be typically
60 ps, where the falling edge of the clock lags the transition edge of the SDOA signal.
4.7.2
Automatic Rate Detection
The reclocker features an Automatic Rate Detector (ARD) circuit that monitors the input signal rate and
automatically sets the reclocker to the correct video rate. The data rate determined by the ARD block may be read
from bits 1:0 in register 89h as shown in Table 4-9.
Table 4-9. Reclocker Rate Detection
Reg89h (Bits 1:0)
Function
00b
Reclocker unlocked
01b
SD rate detected
10b
HD rate detected
11b
3G rate detected (M08045)
M08035, M08045 Data Sheet V1
MACOM™
32
080x5-DSH-001