LTC3838-2_15 Datasheet, PDF (44/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
• The top N-channel MOSFETs of the two channels have
to be located within a short distance from (preferably
<1cm) each other with a common drain connection at
C_IN. Do not attempt to split the input decoupling for the
two channels as it can result in a large resonant loop.
• Connect the input capacitor(s), C_IN, close to the power
MOSFETs. This capacitor provides the MOSFET transient
spike current. Connect the drain of the top MOSFET as
close as possible to the (+) plate of the ceramic portion
of input capacitors C_IN. Connect the source of the bot-
tom MOSFET as close as possible to the (–) terminal
of the same ceramic C_IN capacitor(s). These ceramic
capacitor(s) bypass the high di/dt current locally, and
both top and bottom MOSFET should have short PCB
trace lengths to minimize high frequency EMI and
prevent MOSFET voltage stress from inductive ringing.
• The path formed by the top and bottom N-channel
MOSFETs, and the C_IN capacitors should have short
leads and PCB trace. The (–) terminal of output capaci-
tors should be connected close to the (–) terminal of
C_IN, but away from the loop described above. This is to
achieve an effect of Kelvin (4-wire) connection to the
input ground so that the “chopped” switching current
will not flow through the path between the input ground
and the output ground, and cause common mode output
voltage ripple.
• Several smaller sized ceramic output capacitors, C_OUT ,
can be placed close to the sense resistors and before
the rest bulk output capacitors.
• The filter capacitor between the SENSE⁺ and SENSE^– pins
should always be as close as possible to these pins.
Ensure accurate current sensing with Kelvin (4-wire)
connections to the soldering pads from underneath
the sense resistors or inductor. A pair of sense traces
should be routed together with minimum spacing.
R_SENSE, if used, should be connected to the inductor
on the noiseless output side, and its filter resistors
close to the SENSE⁺/SENSE^– pins. For DCR sensing,
however, filter resistor should be placed close to the
inductor, and away from the SENSE⁺/SENSE^– pins, as
its terminal is the SW node.
• Keep small-signal components connected noise-sensi-
tive pins (give priority to SENSE⁺/SENSE^–, V_OUTSENSE1+/
V_{OUTSENSE1–}, V_DFB2+/V_DFB2–, RT, ITH, etc.) on the left
hand side of the IC as close to their respective pins as
possible. This minimizes the possibility of noise coupling
into these pins. If the LTC3838-2 can be placed on the
bottom side of a multilayer board, use ground planes
to isolate from the major power components on the top
side of the board, and prevent noise coupling to noise
sensitive components on the bottom side.
• Place the resistor feedback dividers close to the
V_OUTSENSE1+ and V_{OUTSENSE1–} pins for channel 1, or
the V_DFB2+ and V_DFB2– pins for channel 2, so that the
feedback voltage tapped from the resistor divider will
not be disturbed by noise sources. Route remote sense
PCB traces (use a pair of wires closely together for
differential sensing) directly to the terminals of output
capacitors for best output regulation.
• Place decoupling capacitors C_ITH2 next to the ITH and
SGND pins with short, direct trace connections.
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor C_INTVCC between
the INTV_CC pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor C_DRVCC close
to the IC, between the combined DRV_CC1,2 pins and
PGND.
• Filter the V_IN input to the LTC3838-2 with an RC filter.
Place the filter capacitor close to the V_IN pin.
• If vias have to be used, use immediate vias to con-
nect components to the SGND and PGND planes of
LTC3838‑2. Use multiple large vias for power compo-
nents.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.
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