LTC3838-2_15 Datasheet, PDF (43/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
To set up the detect transient (DTR) feature, pick resis-
tors for an equivalent R_ITH = R_ITH1//R_ITH2 close to 40k.
Here, 1% resistors R_ITH1 = 90.9k (low side) and R_ITH2 =
82.5k (high side) are used, which yields an equivalent
R_ITH of 43.2k, and a DC-bias threshold of 236mV typical
above one-half of INTV_CC (including the 2.5µA pull-up
current from the DTR pin, see the Load-Release Transient
Detection section). Note that even though the accuracy
of the equivalent compensation resistance R_ITH is not as
important, always use 1% or better resistors for the resis-
tor divider from INTV_CC to SGND to guarantee the relative
accuracy of this DC-bias threshold. To disable the DTR
feature, simply use a single R_ITH resistor to SGND, and
tie the DTR pin to INTV_CC.
If channel 2 uses an external reference voltage with a ratio
of V_OUT2: V_EXTVREF2 = 2:1, as in this design example, it
would have the same ratio and overall system gain as
channel 1 (V_OUT1: V_INTVREF = 1.2V: 0.6V = 2:1), there-
fore the same values (as channel 1) of compensation
components can be used on ITH2 pin. If another ratio is
needed, the ITH compensation may need to be adjusted.
Figure 17 shows an R_SENSE and DTR-disabled version of
this design with a channel 2 that has V_OUT2: V_EXTVREF2 =
1:1. Note that as EXTV_REF2 is getting closer to its higher
limit , the lower end of the V_IN range may require a higher
value to guarantee the INTV_CC required at the EXTV_REF2
applied (see the Electrical Characteristics section) and
assure TRACK/SS2 settles well above EXTV_REF2 when no
external pull-up is used.
PCB Layout Checklist
The printed circuit board layout is illustrated graphically
in Figure 14. Figure 15 illustrates the current waveforms
present in the various branches of 2-phase synchronous
regulators operating in continuous mode. Use the follow-
ing checklist to ensure proper operation:
• A multilayer printed circuit board with dedicated ground
planes is generally preferred to reduce noise coupling
and improve heat sinking. The ground plane layer
should be immediately next to the routing layer for the
power components, e.g., MOSFETs, inductors, sense
resistors, input and output capacitors etc.
• Keep SGND and PGND separate. Upon finishing the
layout, connect SGND and PGND together with a single
PCB trace underneath the IC from the SGND pin through
the exposed PGND pad to the PGND pin.
• All power train components should be referenced to
PGND; all components connected to noise-sensitive
pins, e.g., ITH, RT, TRACK/SS, etc., should return to the
SGND pin. Keep PGND ample, but SGND area compact.
Use a modified “star ground” technique: a low imped-
ance, large copper area central PCB point on the same
side of the as the input and output capacitors.
• Place power components, such as C_IN, C_OUT , MOSFETs,
D_B and inductors, in one compact area. Use wide but
shortest possible traces for high current paths (e.g., V_IN,
V_OUT , PGND etc.) to this area to minimize copper loss.
• Keep the switch nodes (SW1,2), top gates (TG1,2) and
boost nodes (BOOST1,2) away from noise-sensitive
small-signal nodes, especially from the opposite chan-
nel’s voltage and current sensing feedback pins. These
nodes have very large and fast moving signals and
therefore should be kept on the “output side” of the
LTC3838-2 (power-related pins are toward the right
hand side of the IC), and occupy minimum PC trace
area. Use compact switch node (SW) planes to improve
cooling of the MOSFETs and to keep EMI down. If DCR
sensing is used, place the top filter resistor (R1 only in
Figure 5) close to the switch node.
For more information www.linear.com/3838-2
38382f
43