LTC3838-2_15 Datasheet, PDF (42/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
Use an additional resistor in the DCR filter, as discussed
in DCR Inductor Current Sensing, to scale the V_SENSE(MAX)
down by a comfortable margin below the lower limit of
the LTC3838-2’s own V_SENSE(MAX) specification, so that
the maximum output current can be guaranteed.
In this design example, a 3.57k and 15k resistor divider
is used. The previously calculated V_SENSE(MAX) is scaled
down from 28mV to 22.6mV, which is close to the lower
limit of LTC3838-2’s V_SENSE(MAX) specification. Note the
equivalent R_DCR = 3.57k//15k = 2.9k, slightly lower than
the 3.1k calculated above for a matched R_DCR-C_DCR and
L-DCR network. The resulted mismatch allows for a slightly
higher ripple in V_SENSE.
Remember to check the maximum possible peak inductor
current, considering the upper spec limit of V_SENSE(MAX)
and the DCR_(MIN) at lowest operating temperature, as well
as the maximum ∆I_L, is not going to saturate the inductor
or exceed the rating of power MOSFETs:
I_{L(PEAK )}
=
V_SENSE(MAX)(Upper SpecLimit)
DCR_MIN ^1+ ₍T_MIN – 25°C₎ • 0.4% /
°C^
+
∆I_{L(MAX )}
For the external N-channel MOSFETs, Renesas
RJK0305DBP (R_DS(ON) = 13mΩ max, C_MILLER =
150pF, V_GS = 4.5V, θ_JA = 40°C/W, T_J(MAX) = 150°C)
is chosen for the top MOSFET (main switch). RJK-
0330DBP (R_DS(ON) = 3.9mΩ max, V_GS = 4.5V, θ_JA =
40°C/W, T_J(MAX) = 150°C) is chosen for the bottom
MOSFET (synchronous switch). The power dissipation
for each MOSFET can be calculated for V_IN = 24V and
typical T_J = 125°C:
P_TOP
=
 1.2V
 24V


(15A)²
(13mΩ)^1+
0.4%₍125°C
–
25°C₎^
+
(24V)²


15A
2


(150pF)^{}
2.5Ω
5.3V – 3V
+
1.2Ω
3V
_(350kHz)
= 0.54W
P_BOT
=


24V – 1.2V
24V
_(15A)2
(3.9mΩ)^1+
0.4%₍125°C
–
25°C₎^
= 1.2W
The resulted junction temperatures at an ambient tem-
perature T_A = 75°C are:
T_J(TOP) = 75°C + (0.54W)(40°C/W) = 97°C
T_J(BOT) = 75°C + (1.2W)(40°C/W) = 123°C
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select the C_IN capacitors to give ample capacitance and
RMS ripple current rating. Consider worst-case duty
cycles per Figure 6: If operated at steady-state with SW
nodes fully interleaved, the two channels would gener-
ate not more than 7.5A RMS at full load. In this design
example, 3 × 10µF 35V X5R ceramic capacitors are put
in parallel to take the RMS ripple current, with a 220µF
aluminum-electrolytic bulk capacitor for stability. For
10µF 1210 X5R ceramic capacitors, try to keep the ripple
current less than 3A RMS through each device. The bulk
capacitor is chosen for RMS rating per simulation with
the circuit model provided.
The output capacitor C_OUT is chosen for a low ESR of
4.5mΩ to minimize output voltage changes due to inductor
ripple current and load steps. The output voltage ripple
is given as:
∆V_OUT(RIPPLE) = ∆I_L(MAX) • ESR = 5.85A • 4.5mΩ = 26mV
However, a 10A load step will cause an output change
of up to:
∆V_OUT(STEP) = ∆I_LOAD • ESR = 10A • 4.5mΩ = 45mV
Optional 2 × 100µF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
The ITH compensation resistor R_ITH of 40k and a C_ITH of
220pF are chosen empirically for fast transient response,
and an additional C_ITH2 = 22pF is added directly from ITH pin
to SGND, to roll off the system gain at switching frequency
and attenuate high frequency noise. For less aggressive
transient response but more stability, lower-valued R_ITH
and higher-valued C_ITH and C_ITH2 can be used (such as
the various combinations used in Figures 16, 17, 18, 19,
20), which typically results in lower bandwidth but more
phase margin.
42
For more information www.linear.com/3838-2
38382f