LTC3838-2_15 Datasheet, PDF (28/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
cycle. This graph can be used to estimate the maximum
RMS capacitor current for a multiple-phase application,
assuming the channels are identical and their phases are
fully interleaved.
Figure 7 shows that the use of more phases will reduce the
ripple current through the input capacitors due to ripple
current cancellation. However, since LTC3838-2 is only
truly phase-interleaved at steady state, transient RMS cur-
rents could be higher than the curves for the designated
number of phase. Therefore, it is advisable to choose
capacitors by taking account the specific load situations
of the applications. It is always the safest to choose input
capacitors’ RMS current rating closer to the worst case of
a single-phase application discussed above, calculated by
assuming the loss that would have resulted if controller
channels switched on at the same time.
0.6
0.5
0.4
1-PHASE
2-PHASE
3-PHASE
0.3
4-PHASE
6-PHASE
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_O/V_IN)
38382 F07
Figure 7. Normalized RMS Input Ripple Current
However, it is generally not needed to size the input capaci-
tor for such worst-case conditions where on-times of the
phases coincide all the time. During a load step event, the
overlap of on-time will only occur for a small percentage
of time, especially when duty cycles are low. A transient
event where the switch nodes align for several cycles at
a time should not damage the capacitor. In most applica-
tions, sizing the input capacitors for 100% steady-state
load should be adequate. For example, a microprocessor
load may cause frequent overlap of the on-times, which
makes the ripple current higher, but the load current may
rarely be at 100% of I_OUT(MAX). Using the worst-case load
current should already have margin built in for transient
conditions.
The V_IN sources of the top MOSFETs should be placed
close to each other and share common C_IN(s). Separating
the sources and C_IN may produce undesirable voltage and
current resonances at V_IN.
A small (0.1µF to 1µF) bypass capacitor between the IC’s
V_IN pin and ground, placed close to the IC, is suggested.
A 2.2Ω to 10Ω resistor placed between C_IN and the V_IN
pin is also recommended as it provides further isolation
from switching noise of the two channels.
C_OUT Selection
The selection of output capacitance C_OUT is primarily
determined by the effective series resistance, ESR, to
minimize voltage ripple. The output voltage ripple ∆V_OUT ,
in continuous mode is determined by:
∆V_OUT
≤
∆I_L

^RESR
+
8
•
f
1
• C_OUT



where f is operating frequency, and ∆I_L is ripple current
in the inductor. The output ripple is highest at maximum
input voltage since ∆I_L increases with input voltage. Typi-
cally, once the ESR requirement for C_OUT has been met,
the RMS current rating generally far exceeds that required
from ripple current.
In multiphase single-output applications, it is advisable to
consider ripple requirements at specific load conditions. At
steady state, the LTC3838-2’s individual phases are inter-
leaved, and their ripples cancel each other at the output,
so ripple on C_OUT is reduced. During transient, when the
phases are not fully interleaved, the ripple cancellation
may not be as effective. While the worst-case ∆I_L is the
sum of the ∆I_Ls of individual phases aligned during a
fast transient, such ripple tends to counteract the effect
of load transient itself and lasts for only a short time. For
example, during sudden load current increase, the phases
align to ramp up the total inductor current to quickly pull
the V_OUT up from the droop.
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