LTC3838-2_15 Datasheet, PDF (14/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3838-2 is a controlled on-time, valley current
mode step-down DC/DC dual controller with two channels
operating out of phase. Each channel drives both main
and synchronous N-channel MOSFETs. The two channels
can be either configured to two independently regulated
outputs, or combined into a single output.
The top MOSFET is turned on for a time interval determined
by a one-shot timer. The duration of the one-shot timer is
controlled to maintain a fixed switching frequency. As the
top MOSFET is turned off, the bottom MOSFET is turned
on after a small delay. The delay, or dead time, is to avoid
both top and bottom MOSFETs being on at the same time,
causing shoot-through current from V_IN directly to power
ground. The next switching cycle is initiated when the cur-
rent comparator, I_CMP, senses that inductor current falls
below the trip level set by voltages at the ITH and V_RNG
pins. The bottom MOSFET is turned off immediately and
the top MOSFET on again, restarting the one-shot timer
and repeating the cycle. In order to avoid shoot-through
current, there is also a small dead-time delay before the
top MOSFET turns on. At this moment, the inductor cur-
rent hits its “valley” and starts to rise again.
Inductor current is determined by sensing the voltage
between SENSE⁺ and SENSE^–, either by using an explicit
resistor connected in series with the inductor or by implicitly
sensing the inductor’s DC resistive (DCR) voltage drop
through an RC filter connected across the inductor. The
trip level of the current comparator, I_CMP , is proportional
to the voltage at the ITH pin, with a zero-current threshold
corresponding to an ITH voltage of around 0.8V.
The error amplifier (EA) adjusts this ITH voltage by compar-
ing the feedback signal (V_FB) derived from the difference
amplifier (DIFFAMP) to an internal or external reference
voltage. The ITH voltage controls the output by adjusting
the current in the inductor. Output voltage is regulated so
that the feedback voltage is equal to the reference. If the
load current increases/decreases, it causes a momentary
drop/rise in the differential feedback voltage relative to
the reference. The EA then moves ITH voltage, or induc-
tor valley current setpoint, higher/lower until the average
inductor current again matches the load current, so that
the output voltage comes back to the regulated voltage.
The LTC3838-2 features a detect transient (DTR) pin to
detect “load-release”, or a transient where the load current
suddenly drops, by monitoring the first derivative of the
ITH voltage. When detected, the bottom gate (BG) is turned
off and inductor current flows through the body diode in
the bottom MOSFET, allowing the SW node voltage to
drop below PGND by the body diode’s forward-conduction
voltage. This creates a more negative differential voltage
(V_SW – V_OUT) across the inductor, allowing the inductor
current to drop faster to zero, thus creating less overshoot
on V_OUT. See Load-Release Transient Detection in Applica-
tions Information for details.
Differential Output Sensing and External Reference
Both channels of this dual controller have differential
output voltage sensing. The output voltage is resistively
divided externally to create a feedback voltage for the
controller. As shown in the Functional Diagram, channel 1
uses an external 2-resistor voltage divider, and an internal
unity-gain difference amplifier (DIFFAMP) that converts
the differential feedback signal to a single-ended internal
feedback voltage V_FB1 = V_OUTSENSE1+ – V_{OUTSENSE1–}
with respect to SGND. With the external resistor di-
vider, V_OUT1+– V_OUT1– = V_FB1 • (R_FB1 + R_FB2)/R_FB1.
Channel 2 has a unique feedback amplifier that produces
V_FB2 = 2 • V_DFB2+ – V_DFB2–. Its external feedback network
requires a third resistor tied to the external reference
remote ground (V_REF2–). The third resistor must have a
value equal to the parallel value of the two voltage divider
resistors R_DFB1 and R_DFB2 so that V_OUT2+ – V_OUT2– =
(V_FB2 – V_REF2– ) • (R_DFB1 + R_DFB2)/R_DFB1.
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