LTC3838-2_15 Datasheet, PDF (17/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
OPERATION (Refer to Functional Diagram)
Light Load Current Operation
If the MODE/PLLIN pin is tied to INTV_CC or an external
clock is applied to MODE/PLLIN, the LTC3838-2 will be
forced to operate in continuous mode. With load current
less than one-half of the full load peak-to-peak ripple, the
inductor current valley can drop to zero or become nega-
tive. This allows constant-frequency operation but at the
cost of low efficiency at light loads.
If the MODE/PLLIN pin is left open or connected to signal
ground, the channel will transition into discontinuous mode
operation, where a current reversal comparator (I_REV)
shuts off the bottom MOSFET (M_B) as the inductor current
approaches zero, thus preventing negative inductor current
and improving light-load efficiency. In this mode, both
switches can remain off for extended periods of time. As
the output capacitor discharges by load current and the
output voltage droops lower, EA will eventually move the
ITH voltage above the zero current level (0.8V) to initiate
another switching cycle.
Power Good and Fault Protection
Each PGOOD pin is connected to an internal open-drain
N‑channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., V_OUT1,2 or
DRV_CC). Overvoltage or undervoltage comparators (OV,
UV) turn on the MOSFET and pull the PGOOD pin low
when the feedback voltage is outside the ±7.5% window
of the channel’s reference voltage. The PGOOD pin is
also pulled low when the channel’s RUN pin is below the
1.2V threshold (hysteresis applies), or in undervoltage
lockout (UVLO).
When the feedback voltage is within the ±7.5% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50µs delay before
its PGOOD is pulled low.
In an overvoltage (OV) condition, M_T is turned off and M_B
is turned on immediately without delay and held on until
the overvoltage condition clears. Upon enabling the RUN1
pin, if V_OUT1 is prebiased so that the V_FB1 is at more than
7.5% above the regulated voltage, OV stays triggered and
bottom gate (BG) forced to pull V_OUT1 low until V_FB1 is
~15mV (or ~2.5% of 0.6V internal reference) hysteresis
below the OV threshold. For channel 2, the OV threshold
is set at 7.5% above the voltage on EXTV_REF2 pin, but the
~15mV hysteresis remains the same regardless of the OV
threshold. To ensure that OV and UV thresholds are not
determined by extremely low reference voltages, apply a
stable EXTV_REF2 before enabling RUN2, which also prevents
BG from being turned on, and any prebiased V_OUT2 from
being pulled low upon start-up.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted
to ground. As the feedback approaches 0V, the internal
clamp voltage for the ITH pin drops from 2.4V to around
1.3V, which reduces the inductor valley current level to
about 30% of its maximum value. Foldback current limiting
is disabled at start-up.
For more information www.linear.com/3838-2
38382f
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