LTC3838-2_15 Datasheet, PDF (34/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
still be maintained. For large load current steps with fast
slew rates, phase lock will be lost until the system returns
back to a steady-state condition (see Figure 10). It may
take up to several hundred microseconds to fully resume
the phase lock, but the frequency lock generally recovers
quickly, long before phase lock does.
For light load conditions, the phase and frequency syn-
chronization depends on the MODE/PLLIN pin setting. If
the external clock is applied, synchronization will be active
and switching in continuous mode. If MODE/PLLIN is tied
to INTV_CC, it will operate in forced continuous mode at
the R_T-programmed frequency. If the MODE/PLLIN pin is
tied to SGND, the LTC3838-2 will operate in discontinuous
mode at light load and switch into continuous conduction
at the R_T programmed frequency as load increases. The TG
on-time during discontinuous conduction is intentionally
slightly extended (approximately 1.2 times the continuous
conduction on-time as calculated from V_IN, V_OUT and f) to
create hysteresis at the load-current boundary of continu-
ous/discontinuous conduction.
If an application requires very low (approaching minimum)
on-time, the system may not be able to maintain its full
frequency synchronization range. Getting closer to mini-
mum on-time, it may even lose phase/frequency lock at no
load or light load conditions, under which the SW on-time
is effectively longer than TG on-time due to TG/BG dead
times. This is discussed further under Minimum On-Time,
Minimum Off-Time and Dropout Operation.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration that
LTC3838-2’s TG (top gate) pin can be in high or “on”
state. It has dependency on the operating conditions of the
switching regulator, and is a function of voltages on the
V_IN and V_OUT pins, as well as the value of external resistor
R_T. As shown by the t_ON(MIN) curves in the Typical Perfor-
mance Characteristics section, a minimum on-time of 30ns
can be achieved when V_OUT, sensed by the SENSE^–­ pin,
is at 0.6V or lower, while the V_IN is tied to its maximum
value of 38V. For larger values of V_OUT, smaller values of
V_IN and/or larger values of R_T (i.e. lower f), the minimum
achievable on-time will be longer. The valley mode control
architecture allows low on-time, making the LTC3838-2
suitable for high step-down ratio applications.
The effective on-time, as determined by the SW node
pulse width, can be different from this TG on-time, as it
also depends on external components, as well as loading
conditions of the switching regulator. One of the factors that
contributes to this discrepancy is the characteristics of the
power MOSFETs. For example, if the top power MOSFET’s
turn-on delay is much smaller than the turn-off delay,
the effective on-time will be longer than the TG on-time,
limiting the effective minimum on-time to a larger value.
Light-load operation, in forced continuous mode, will
further elongate the effective on-time due to the dead
times between the “on” states of TG and BG, as shown in
Figure 11. During the dead time from BG turn-off to TG
turn-on, the inductor current flows in the reverse direction,
charging the SW node high before the TG actually turns
on. The reverse current is typically small, causing a slow
rising edge. On the falling edge, after the top FET turns off
and before the bottom FET turns on, the SW node lingers
high for a longer duration due to a smaller peak inductor
current available in light load to pull the SW node low. As
a result of the sluggish SW node rising and falling edges,
the effective on-time is extended and not fully controlled
by the TG on-time. Closer to minimum on-time, this may
cause some phase jitter to appear at light load. As load
current increase, the edges become sharper, and the phase
locking behavior improves.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
D_MIN = f • t_ON(MIN)
where t_ON(MIN) is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint. If the minimum on-time that LTC3838-2 can
provide is longer than the on-time required by the duty
cycle to maintain the switching frequency, the switching
frequency will have to decrease to maintain the duty cycle,
but the output voltage will still remain in regulation. This is
generally more preferable to skipping cycles and causing
larger ripple at the output, which is typically seen in fixed
frequency switching regulators.
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