LTC3838-2_15 Datasheet, PDF (18/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
OPERATION (Refer to Functional Diagram)
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
switching channel is independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector,
and the time interval of the one-shot timer is adjusted on
a cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, R_T , from
the RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3838-2 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
Multichip Operations
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels as
well as the CLKOUT signal, as shown in Table 2. The phases
tabulated are relative to zero degree (0°) being defined as the
rising edge of the internal reference clock signal of channel
1. The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution feeding
either a single high current output, or separate outputs.
The system can be configured for up to 12-phase opera-
tion with a multichip solution. Typical configurations are
shown in Table 3 to interleave the phases of the channels.
Table 2
PHASMD
Channel 1
Channel 2
CLKOUT
SGND
0°
180°
60°
FLOAT
0°
180°
90°
INTV_CC
0°
240°
120°
Table 3
NUMBER OF
PHASES
2
3
4
6
12
NUMBER OF
LTC3838-2
1
2
2
3
6
PIN CONNECTIONS
[PIN NAME (CHIP NUMBER)]
PHASMD(1) = FLOAT or SGND
PHASMD(1) = INTV_CC
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(1) = FLOAT
PHASMD(2) = FLOAT or SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT or SGND
MODE/PLLIN(3) = CLKOUT(2)
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT
MODE/PLLIN(3) = CLKOUT(2)
PHASMD(4) = SGND
MODE/PLLIN(4) = CLKOUT(3)
PHASMD(5) = SGND
MODE/PLLIN(5) = CLKOUT(4)
PHASMD(6) = FLOAT or SGND
MODE/PLLIN(6) = CLKOUT(5)
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