LTC3838-2_15 Datasheet, PDF (38/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
using the same C_ITH1 and make R_ITH1//R_ITH2 equal the
R_ITH as used in conventional single resistor OPTI-LOOP
compensation. This will also provide the R-C time constant
needed for the DTR duration. The DTR sensitivity can be
adjusted by the DC bias voltage difference between DTR
and half INTV_CC. This difference could be set as low as
200mV, as long as the ITH ripple voltage with DC load
current does not trigger the DTR.
Note the internal 2.5µA pull-up current from the DTR pin
will generate an additional offset on top of the resistor
divider itself, making the total difference between the DC
bias voltage on the DTR pin and half INTV_CC:
V_DTR
–
0.5V_INTVCC
= ^{}_(RITH^R_1I+^TH_R^1ITH2₎
–

0.5_
•
5.3V
+ 2.5µA • ₍R_ITH1//R_ITH2)
As illustrated in Figure 12, when load current suddenly
drops, V_OUT overshoots, and ITH drops quickly. The voltage
on the DTR pin will also drop quickly, since it is coupled
to the ITH pin through a capacitor. If the load transient
is fast enough that the DTR voltage drops below half of
INTV_CC, a load release event is detected. The bottom gate
(BG) will be turned off, so that the inductor current flows
through the body diode in the bottom MOSFET. This al-
lows the SW node to drop below PGND by a voltage of
a forward-conducted silicon diode. This creates a more
negative differential voltage (V_SW – V_OUT) across the
inductor, allowing the inductor current to drop at a faster
rate to zero, therefore creating less overshoot on V_OUT.
The DTR comparator output is overridden by reverse
inductor current detection (I_REV) and overvoltage (OV)
condition. This means BG will be turned off when SENSE⁺
is higher than SENSE^– (i.e., inductor current is positive),
as long as the OV condition is not present. When inductor
current drops to zero and starts to reverse, BG will turn
back on in forced continuous mode (e.g., the MODE/
PLLIN pin tied to INTV_CC, or an input clock is present),
even if DTR is still below half INTV_CC. This is to allow the
inductor current to go negative to quickly pull down the
V_OUT overshoot. Of course, if the MODE/PLLIN pin is set
to discontinuous mode (i.e., tied to SGND), BG will stay
off as inductor current reverse, as it would with the DTR
feature disabled.
Also, if V_OUT gets higher than the OV window (7.5%
typical), the DTR function is defeated and BG will turn
on regardless. Therefore, in order for the DTR feature
to reduce V_OUT overshoot effectively,sufficient output
capacitance needs to be used in the application so that
OV is not triggered with the amount of load step desired
to have its overshoot suppressed.
Experimenting with a 0.6V output application (modified
from the design example circuit by setting V_OUT to 0.6V
and ITH compensation adjusted accordingly) shows this
detect transient feature significantly reduces the overshoot
peak voltage, as well as time to resume regulation during
load release steps (see application examples in Typical
Performance Characteristics).
SW
5V/DIV
BG
5V/DIV
DTR
1V/DIV
I_L
10A/DIV
BG TURNS BACK ON, INDUCTOR
CURRENT (I_L) GOES NEGATIVE
DTR DETECTS LOAD
RELEASE, TURNS OFF BG
FOR FASTER INDUCTOR
CURRENT (I_L) DECAY
5µs/DIV
LOAD RELEASE = 15A TO 0A
V_IN = 5V
V_OUT = 0.6V
(12a) DTR Enabled
SW
5V/DIV
BG
5V/DIV
ITH
1V/DIV
BG REMAINS ON
DURING THE LOAD
RELEASE EVENT
I_L
10A/DIV
5µs/DIV
LOAD RELEASE = 15A TO 0A
V_IN = 5V
V_OUT = 0.6V
(12b) DTR Disabled
38382 F12
Figure 12. Comparison of V_OUT Overshoot with Detect Transient (DTR) Feature Enabled and Disabled
38
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38382f