LTC3838-2_15 Datasheet, PDF (35/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
APPLICATIONS INFORMATION
TG-SW
(V_GS OF TOP
MOSFET)
BG
(V_GS OF
BOTTOM
MOSFET)
I_L 0
V_IN
SW
DEAD-TIME
DELAYS
NEGATIVE
INDUCTOR
CURRENT
IN FCM
DURING BG-TG DEAD TIME,
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
I_L
+– _VIN
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
L
L
SW
I_L
TOTAL CAPACITANCE
ON THE SW NODE
38382 F11
Figure 11. Light Loading On-Time Extension for Forced
Continuous Mode Operation
The t_ON(MIN) curves in the Typical Performance Charac-
teristics are measured with minimum load on TG and
BG, at extreme cases of V_IN = 38V, and/or V_OUT = 0.6V,
and/or programmed f = 2MHz (i.e., R_T = 18k). In applica-
tions with different V_IN, V_OUT and/or f, the t_ON(MIN) that
can be achieved will generally be larger. Also, to guarantee
frequency and phase locking at light load, sufficient margin
needs to be added to account for the dead times (t_D(TG/BG)
+ t_D(TG/BG) in the Electrical Characteristics).
For applications that require relatively low on-time, proper
caution has to be taken when choosing the power MOSFET.
If the gate of the MOSFET is not able to fully turn on due
to insufficient on-time, there could be significant heat dis-
sipation and efficiency loss as a result of larger R_DS(ON).
This may even cause early failure of the power MOSFET.
The minimum off-time is the smallest duration of time
that the TG pin can be turned low and then immediately
turned back high. This minimum off-time includes the time
to turn on the BG (bottom gate) and turn it back off, plus
the dead-time delays from TG off to BG on and from BG
off to TG on. The minimum off-time that the LTC3838-2
can achieve is 90ns.
The effective minimum off-time of the switching regulator,
or the shortest period of time that the SW node can stay
low, can be different from this minimum off-time. The main
factor impacting the effective minimum off-time is the top
and bottom power MOSFETs’ electrical characteristics,
such as Qg and turn-on/off delays. These characteristics
can either extend or shorten the SW nodes’ effective
minimum off-time. Large size (high Qg) power MOSFETs
generally tend to increase the effective minimum off-time
due to longer gate charging and discharging times. On
the other hand, imbalances in turn-on and turn-off delays
could reduce the effective minimum off-time.
The minimum off-time limit imposes a maximum duty
cycle of:
D_MAX = 1 – f • t_OFF(MIN)
where t_OFF(MIN) is the effective minimum off-time of the
switching regulator. Reducing the operating frequency can
alleviate the maximum duty cycle constraint.
If the maximum duty cycle is reached, due to a drooping
input voltage for example, the output will drop out of
regulation. The minimum input voltage to avoid dropout is:
V_IN(MIN)
=
V_OUT
D_MAX
At the onset of drop-out, there is a region of V_IN of about
500mV that generates two discrete off-times, one being
the minimum off time and the other being an off-time that
is about 40ns to 60ns longer than the minimum off-time.
This secondary off-time is due to the extra delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output in
regulation. There may be higher SW node jitter, apparent
especially when synchronized to an external clock, but the
output voltage ripple remains relatively small.
For more information www.linear.com/3838-2
38382f
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