LTC3838-2_15 Datasheet, PDF (19/56 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with xternal Reference Voltage and Dual Differential Output Sensing

LTC3838-2
OPERATION (Refer to Functional Diagram)
Single-Output External-Reference PolyPhase
Configurations
To use LTC3838-2 for a 2-phase single output external-
referenced step-down controller: Tie the V_OUTSENSE1+ pin
to INTV_CC, which will disable channel 1’s error amplifier
and internally connect ITH2 to ITH1. Tie the compensa-
tion R-C components to the ITH2 pin. The ITH1 pin can
be either left open or shorted to ITH2 externally. The
TRACK/SS1 and PGOOD1 pins become defunct and
can be left open. Note that the RUN1 and RUN2, as
well as DTR1 and DTR2 pins still function for the two
channels individually, therefore should be shorted ex-
ternally for single-output applications. Set PHASMD
to SGND or FLOAT so that the two channels are 180°
out-of-phase. Efficiency losses may be substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A 2-phase implementation can reduce the input
path power loss by up to 75%.
To make a single-output converter of three or more phases,
additional LTC3838-2 ICs can be used. The first chip should
be tied the same way as the 2-phase above. If only one
more channel of an additional LTC3838-2 is needed, use
channel 2 for the additional phase:
• Tie the ITH2 pin to the ITH2 pin of the first chip
• Tie the RUN2 pin to the RUN pins of the first chip
• Tie the V_DFB2+ pin to the V_DFB2+ pin of the first chip
• Tie the V_DFB2– pin to the V_DFB2– pin of the first chip
• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the
first chip
If both channels are needed, the additional LTC3838-2
chip should be tied the same way as the first LTC3838-2
chip to disable channel 1’s EA:
• Tie the V_OUTSENSE1+ pin to the chip’s own INTV_CC
• Tie the ITH2 pin to the ITH2 pin of the first chip
• Tie the RUN pins to the RUN pins of the first chip
• Tie the V_DFB2+ pin to the V_DFB2+ pin of the first chip
• Tie the V_DFB2– pin to the V_DFB2– pin of the first chip
• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the
first chip
For more information www.linear.com/3838-2
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