IS66WVD1M16ALL Datasheet, PDF (9/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Burst Read Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a READ (WE# = HIGH, Figure 2)
Then the data needs to be output to multiplexed data bus (ADQ0~ADQ15)
according to set WAIT states.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of a row, unless wrapping within the burst length.
A full 4 word synchronous read access is shown in Figure 2 and the AC characteristics are specified
in Table 16.
Figure 2. Synchronous Read Access Timing
t_ABA
CLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
VALID
ADDRESS
t_SP
t_HD
VALID
ADDRESS
t_SP
t_HD
t_CSP
t_SP
t_SP t_HD
OE#
t_KW
WAIT ^HiZ
t_ACLK
t_KOH
VALID
OUTPUT
VALID
OUTPUT
t_CEM
t_OLZ
t_OE
t_KW
t_CLK
VALID
OUTPUT
VALID
OUTPUT
t_HZ
t_HD t_CBPH
t_HD
t_OHZ
t_WZ
Read Burst Identified (WE#=HIGH)
Rev. A | July 2013
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