IS66WVD1M16ALL Datasheet, PDF (47/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Figure 32: Burst WRITE followed by Burst READ
CLK
t_CLK
t_ABA
Address
ADQ0-
ADQ15
ADV#
VALID
ADDRESS
t_SP t_HD
VALID
ADDRESS
t_AS
t_AS
t_CSP
CE#
UB#/LB#
WE#
t_SP ^tHD
OE#
t_KW
WAIT ^HiZ
t_SP t_HD
VALID
ADDRESS
t_SP t_HD
DATA IN DATA IN DATA INDATA IN
VALID
ADDRESS
t_ACLK t_KOH
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
t_CEM
t_SPt_HD
t_CBPH
t_CEM
t_HD
t_OLZ
t_OHZ
t_OE
t_WZ
HiZ ^tKW
t_KW
t_KW
Notes:
1. Non-default BCR settings for burst WRITE followed by burst READ; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. A refresh opportunity must be provided every tCEM by taking CE# HIGH.
Rev. A | July 2013
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