IS66WVD1M16ALL Datasheet, PDF (42/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Figure 27: Burst READ at End of Row (Wrap Off)
t_CLK
CLK
Address
ADQ0-
ADQ15
VALID
OUTPUT
ADV# VIH
VIH
CE#
VIL
VALID
OUTPUT
VALID
OUTPUT
End of Row (A[7:0]=FFh)
NOTE2
t_HZ
UB#/LB# VIL
WE#
OE# VIL
WAIT
t_KW t_HZ
Notes:
1. Non-default BCR settings for burst READ at end of row: fixed or variable latency; WAIT
active LOW; WAIT asserted during delay.
2. For burst READs, CE# must go HIGH before the third CLK after the WAIT period begins
(before the third CLK after WAIT asserts with BCR[8] = 0, or before the fourth CLK after
WAIT asserts with BCR[8] = 1).
Rev. A | July 2013
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