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| IS66WVD1M16ALL Datasheet, PDF (39/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation | |||
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IS66WVD1M16ALL
Figure 24: Single Access Burst READ Operation â Fixed Latency
CLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
VALID
ADDRESS
tSP
tHD
VALID
ADDRESS
tSP
tHD
tCSP
tSP
tSP tHD
OE#
tKW
WAIT HiZ
tAA
tAADV
tCO
tCEM
tCLK
tKOH
VALID
OUTPUT
tHD tHZ
tHD
tOLZ
tOE
tKW
tOHZ
tWZ
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default fixed latency BCR settings for single-access burst READ operation: Fixed Latency;
Latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
Rev. A | July 2013
www.issi.com - SRAM@issi.com
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