IS66WVD1M16ALL Datasheet, PDF (15/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash devices. The
refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during
power-up, and can be updated any time the devices are operating in a standby state.
A DIDR provides information on the device manufacturer, CellularRAM generation, and
the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation
when the configuration register enable (CRE) input is HIGH (see Figures 6 through 9).
When CRE is LOW, a READ or WRITE operation will access the memory array. The register
values are written as an address (ADV# LOW) on the ADQ pins.
In an asynchronous WRITE, the values are latched into the configuration register
on the rising edge of CE# or WE#, whichever occurs first; UB#/LB# are “Don’t Care.”
The BCR is accessed when A[19:18] is 10b; the RCR is accessed when A[19:18] is 00b; the
DIDR is accessed when A[19:18] is 01b. For READs, address inputs other than A[19:18]
are “Don’t Care,” and register bits are output as data (ADV# HIGH) on ADQ.
Figure 6: Configuration Register WRITE
– Asynchronous Mode Followed by READ ARRAY Operation
Address
ADQ0-
ADQ15¹
ADV#
CE#
OPCODE
t_AVS t_AVH
OPCODE
t_VS
t_VP
t_CVP
t_CW
VALID
ADDRESS
t_AVS t_AVH
VALID
ADDRESS
t_AADV
t_VP
VALID
OUTPUT
t_HZ
t_CPH
t_CPP
t_CO
UB#/LB#
t_BA
WE#
OE#
CRE²
t_WP
Write Address Bus
Value to Control
Register
t_AVS
t_AVH
t_OLZ
t_OE
Notes:
1. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0].
2. CRE must be HIGH to access registers.
Rev. A | July 2013
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