IS66WVD1M16ALL Datasheet, PDF (31/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Table16 . Burst READ Cycle Timing Requirements
Symbol
Parameter
-7013
-7010
-7008
Unit Note
Min Max Min Max Min Max
t_AA
Address Acess Time (Fixed Latency)
70
70
70
ns
t_AADV
ADV# Access Time (Fixed Latency)
70
70
70
ns
t_ABA
Burst to READ Access Time
(Variable Latency)
35.5
35.9
46.5
ns
t_ACLK
t_CBPH
CLK to Output Delay
CE# High between Subsequent
Burst or Mixed-Mode Operations
5.5
7
9
ns
1
5
5
6
ns
2
t_CEM
Maximum CE# Pulse width
t_CLK
CLK Period
t_CO
Chip Select Access Time (Fixed
Latency)
4
4
4
us
2
7.5
9.62
12.5
ns
70
70
70
ns
t_CSP
CE# Setup Time to Active CLK Edge 2.5
3
4
ns
t_HD
Hold Time from Active CLK Edge
2
2
2
ns
t_HZ
Chip Disable to High-Z Output
7
7
7
ns
3
t_KH/t_KL CLK HIGH or LOW Time
3
3
4
ns
t_KOH
Output Hold from CLK
2
2
2
ns
t_KW
CLK to WAIT Valid
5.5
7
9
ns
1
t_OE
Burst OE# LOW to Output Valid
20
20
20
ns
t_OHZ
OE# high to High-Z Output
7
7
7
ns
4
t_OLZ
OE# low to Low-Z output
3
3
3
ns
4
t_SP
Setup time to Active CLK Edge
2
3
3
ns
t_T
CLK Rise or Fall Time
1.2
1.6
1.8
ns
t_WZ
CE# high to WAIT High-Z
7
7
7
ns
3
Notes:
1. tACLK and tKW values for -7013 are for variable LC = 4 and fixed LC = 8 only. For other LC
settings, these parameters will be 7ns for -7013 devices.
2. A refresh opportunity must be provided every tCEM by taking CE# HIGH.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 16.
The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
Rev. A | July 2013
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