IS66WVD1M16ALL Datasheet, PDF (32/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Table17 . Asynchronous WRITE Cycle Timing Requirements
Symbol
Parameter
t_AS
Address and ADV# LOW Setup Time
t_AVH
Address hold from ADV# HIGH
t_AVS
Address setup to ADV# HIGH
t_AW
Address Valid to End of Write
t_BW
UB#, LB# Select to End of Write
t_CPH
CE# HIGH between Subsequent Asynchronous cycles
t_CVP
CE# low to ADV# HIGH
t_CW
Chip Enable to End of Write
t_DH
Data Hold from Write Time
t_DS
Data Write Setup Time
t_VP
ADV# Low pulse width
t_VS
ADV# Setup to End of Write
t_WHZ
WRITE to ADQ High-Z Output
t_WP
WRITE Pulse Width
t_WR
WRITE Recovery Time
t_WZ
CE# high to WAIT High-Z
-70
Unit
Min Max
0
ns
2
ns
5
ns
70
ns
70
ns
5
ns
7
ns
70
0
ns
20
7
ns
70
ns
7
ns
45
ns
0
ns
7
ns
Notes:
1. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
Notes
1
2
Rev. A | July 2013
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