IS66WVD1M16ALL Datasheet, PDF (48/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Figure 33: Asynchronous WRITE followed by Burst READ
CLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
t_AW
VALID
ADDRESS
t_AVS t_AVH
VALID
ADDRESS
t_VS
t_VP
t_CSP
t_CW
t_BW
t_DS t_DH
VALID
DATA
VALID
ADDRESS
t_SP t_HD
VALID
ADDRESS
NOTE2
t_CBPH
t_SP t_HD
t_CSP
t_SP
t_WP
t_WR
OE#
WAIT ^HiZ
t_CLK
t_ACLK
t_KOH
VALID
OUTPUT
t_HD
t_HD
t_OLZ
t_OE
t_WZ
t_KW
Notes:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous WRITE and variable-latency burst READ operations,
CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs.
A refresh opportunity must be provided every tCEM by taking CE# HIGH.
Rev. A | July 2013
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