IS66WVD1M16ALL Datasheet, PDF (11/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD1M16ALL
Asynchronous Mode
Asynchronous mode uses industry-standard SRAM control signals (CE#, ADV#, OE#,
WE#, UB#, and LB#). READ operations (Figure 4) are initiated by bringing CE#, ADV#,
UB# and LB# LOW while keeping OE# and WE# HIGH, and driving the address onto the
multiplexed address/data bus. ADV# is taken HIGH to capture the address, and OE# is
taken LOW. Valid data will be driven out of the I/Os after the specified access time has
elapsed.
WRITE operations (Figure 5) occur when CE#, ADV#, WE#, UB#, and LB# are driven LOW
with the address on the multiplexed address/data bus. ADV# is taken HIGH to capture
the address, then the write data is driven onto the bus. During asynchronous WRITE
operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE#
must be HIGH while the address is driven onto the ADQ bus. The data to be written is
latched on the rising edge of CE#, WE#, UB#, and LB# (whichever occurs first).
During asynchronous operation, the CLK input must be held LOW. WAIT will be driven
during asynchronous READs, and its state should be ignored. WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing
Address
ADQ0-
ADQ15
ADV#
CE#
t_AA
VALID
ADDRESS
t_AVS
t_AVH
VALID
ADDRESS
t_VP
t_AADV
t_CVP
t_CO
UB#/LB#
OE#
t_BA
t_OLZ
t_OE
VALID
OUTPUT
t_WZ
t_HZ
t_BHZ
t_OHZ
WE#
t_OEW
HiZ
HiZ
WAIT
Rev. A | July 2013
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