IS61QDB42M36 Datasheet, PDF (7/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Q
I³
State Diagram
Power-Up
Read NOP
Read
Read
Read
D count = 2
Load New
Read Address
D count = 0
Always
Read
D count = 2
DDR-II Read
D count =
D count + 1
Read
D count = 1
Always
Increment
Read Address
Write
Write NOP
Write
Load New
Write Address
D count = 0
Always
Write
D count = 2
DDR-II Write
D count =
D count + 1
Write
D count = 1
Always
Increment
Write Address
Write
D count = 2
Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst addresses are
A0+1, A0+2, and A0+3
2. Read refers to read active status with R = low. Read r.efers to read inactive status with R = high.
3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
Integrated Silicon Solution, Inc.
7
Rev. 
11/10/09