IS61QDB42M36 Datasheet, PDF (14/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Capacitance (T_A = 0 to + 70 C, V_DD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Input capacitance
Data-in capacitance (D0–D35)
Data-out capacitance (Q0–Q35)
Clocks Capacitance (K, K, C, C)
C_IN
C_DIN
C_OUT
C CLK
V_IN = 0V
V_DIN = 0V
V_OUT = 0V
V_CLK = 0V
Maximum
4
4
4
4
Units
pF
pF
pF
pF
DC Electrical Characteristics (T_A = 0 to + 70 C, V_DD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum Maximum
x36 average power supply operating current
(I_OUT = 0, V_IN = V_IH or V_IL)
I_{DD 33}
I_{DD 40}
I_DD50
950
—
850
750
x18 average power supply operating current
(I_OUT = 0, V_IN = V_IH or V_IL)
I_{DD 33}
I_{DD 40}
I_DD50
900
—
800
700
Power supply standby current
(R = V_IH, W = V_IH. All other inputs = V_IH or V_IH, I_IH = 0)
Input leakage current, any input (except JTAG)
(V_IN = V_SS or V_DD)
Output leakage current
(V_OUT = V_SS or V_DDQ, Q in High-Z)
Output “high” level voltage (I_OH = -6mA)
Output “low” level voltage (I_OL = +6mA)
JTAG leakage current
(V_IN = V_SS or V_DD)
1. I_OUT = chip output current.
2. Minimum impedance output driver.
3. JEDEC Standard JESD8-6 Class 1 compatible.
4. For JTAG inputs only.
I_SB
I_LI
I_LO
V_OH
V_OL
I_LIJTAG
—
400
-2
+2
-2
V_DDQ -.4
V_SS
-100
+2
V_DDQ
V_SS+.4
+100
Units
mA
mA
mA
µA
µA
V
V
A
Notes
1
1
1
2, 3
2, 3
4
14
Integrated Silicon Solution, Inc.
Rev. B
11/10/09