IS61QDB42M36 Datasheet, PDF (6/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Application Example
D
Vt
SRAM #1
ZQ R=250Ω
CQ
CQ
Q
D
SRAM #4
R=250Ω
ZQ
CQ
CQ
Q
R ^{SA R W BW0 BW1 C C K K}
SA R W BW₀ BW₁ C C K K
Data In
Data Out
Address
R
W
BW
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Ω Vt=V_REF
Vt
Vt
R
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6
Integrated Silicon Solution, Inc.
Rev. B
11/10/09